zd0305 发表于 2017-3-28 08:39:28

分享:Cadence OrCAD and Allegro 17.20.015 Hotfix


Fixed CCRs: SPB 17.2 HF015    03-16-2017
=================================================================
CCRID                Product       ProductLevel2                Title
=================================================================
1653366 ALLEGRO_EDITOR INTERFACES Unable to attach step model to symbol
1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model
1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function
1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file
1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting Padstack Editor results in incorrectly scaled forms
1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design
1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees
1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.
1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously
1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used
1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places
1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value
1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically
1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad
1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout
1698697 CONCEPT_HDL COPY_PROJECT Copy project corrupts the .dcf file
1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 084
1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position
1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net
1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer
1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation
1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates
1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode

链接：http://pan.baidu.com/s/1kVmHGZ9 密码：smsv

lncwangfeilnc 发表于 2017-3-28 11:11:56

谢谢分享

jack5281206 发表于 2017-3-31 11:24:36

好東西！！ 收下了~~~

happy_andy 发表于 2017-3-31 18:10:53

哎，一个月升了两次，不过还是多升为好！

dansDD 发表于 2017-3-31 18:13:24

好东西，先收藏，谢谢分享！

myin4 发表于 2017-3-31 18:13:37

下来验证一下第二条{:lol:}

NFC 发表于 2017-4-13 20:48:22

费了九牛二虎之力下载，居然装不上。请问你这是可以直接安装的还是啥？我电脑WIN7，32位。

Elec_Ramble 发表于 2017-4-14 09:28:31

NFC 发表于 2017-4-13 20:48
费了九牛二虎之力下载，居然装不上。请问你这是可以直接安装的还是啥？我电脑WIN7，32位。 ...

17应该是只支持64bit了

happy_andy 发表于 2017-4-14 11:33:44

NFC 发表于 2017-4-13 20:48
费了九牛二虎之力下载，居然装不上。请问你这是可以直接安装的还是啥？我电脑WIN7，32位。 ...

17.2 只能安装在64位系统上

happy_andy 发表于 2017-6-5 14:51:03

能否在来个最新的补丁？

fuze2009 发表于 2017-6-13 01:31:36

收藏，谢谢分享。
页: [1]
查看完整版本: 分享:Cadence OrCAD and Allegro 17.20.015 Hotfix