初入FBGA，请教一些SignalTag ii 仿真的问题
程序的功能是：按下key_up 按键，使state +1;其中rst是复位。
此程序下载到板上测试是正常的 。问题是：仿真开始时，开始按下key_up按键，rst信号不知道为什么会出现脉冲，本应该是稳定的电平才对。
本人初入FBGA苦思不知其因。
key_up按键的下降沿作为触发。
程序：
module led_run(rst,mclk,key_up,key_down,key_set,led, seg_led,seg_sel);
input mclk;
input key_up,key_set,key_down;
input rst;
output seg_led;
output seg_sel;
output led;
reg led;
reg state;
reg stateb;
wire clkb;
regseg_led; //数码管的段信号
reg seg_sel; //数码管的选通信号，共4个数码管
reg countb; //数码管显示的频率分频
regkey_count;
reg keyup_r,keydown_r,keyset_r;
reg keyup,keydown,keyset;
initial
begin
led<=4'b0001;
seg_led<=7'b0001000;
seg_sel<=4'b1111 ;
key_count<=15'd0;
countb<=4'd0;
state<=4'd0;
stateb<=2'd0;
end
//10MS ，采样一次按键
always @ (posedge mclk or negedge rst)
begin
if(!rst)
begin
keyup<=1'b1;
keydown<=1'b1;
keyset<=1'b1;
end
else
begin
if(key_count==19'd500000)//约10MS
begin
keyup<=key_up;
keydown<=key_down;
keyset<=key_set;
end
end
end
//每个时钟采样一次
always @ (posedgemclk or negedge rst)
begin
if(!rst)
begin
keyup_r<=1'b1;
keydown_r<=1'b1;
keyset_r<=1'b1;
end
else
begin
keyup_r<=keyup;
keydown_r<=keydown;
keyset_r<=keyset;
end
end
wire keyup_flag,keydown_flag,keyset_flag;
assign keyup_flag = keyup_r& ( ~keyup );
assignkeydown_flag = keydown_r& ( ~keydown );
assignkeyset_flag = keyset_r& ( ~keyset );
always @ (posedgemclk or negedge rst) //时钟产生
begin
if(!rst)
key_count<=19'd0;
else
begin
if(key_count==19'd500000)
key_count<=19'd0;
else
key_count<=key_count+1'd1;
end
end
always @ (posedgemclk or negedge rst)//按键+ -操作
begin
if(!rst)
countb <=5'd0;
else
countb=countb+5'd1;
end
assign clkb=countb;
always @(posedge mclk or negedge rst)
begin
if(!rst)
begin
state <=0;
end
else
begin
if(keyup_flag)
begin
if(state==4'd9)state=4'd1;
else
state=state+4'd1;
end
if(keydown_flag)
begin
if(state==4'd0)state=4'd9;
else
state=state-4'd1;
end
end
end
always@ (posedge clkb or negedge rst) //数码管扫描
begin
if(!rst)
begin
led<=4'b1111;
seg_led<=7'b0001000;
seg_sel<=4'b1111 ;
stateb<=2'd0;
end
else
begin
//if(keydown_ctr )
// begin
//if(state==9)state=4'd1;
// else
// state=state+4'd1;
// end
case(stateb)
2'd0: beginseg_sel<=4'b0111 ;stateb<=2'd1;end //0
2'd1: beginseg_sel<=4'b1011 ;stateb<=2'd2;end //1
2'd2: beginseg_sel<=4'b1101 ;stateb<=2'd3;end //2
2'd3: beginseg_sel<=4'b1110 ;stateb<=2'd0;end //3
endcase
case(state) // E:B7D:B6C:B5 G:B4 F:B3 B:B2A:B1
4'd0: begin led<=4'b0001;seg_led<=7'b0001000;end //state<=4'd1;end //0
4'd1: begin led<=4'b0010;seg_led<=7'b1101101;end //state<=4'd2;end //1
4'd2: begin led<=4'b0100;seg_led<=7'b0010100;end //state<=4'd3;end //2
4'd3: begin led<=4'b1000;seg_led<=7'b1000100;end //state<=4'd4;end //3
4'd4: begin led<=4'b0100;seg_led<=7'b1100001;end //state<=4'd5;end //4
4'd5: begin led<=4'b0010;seg_led<=7'b1000010;end //state<=4'd6;end //5
4'd6: begin led<=4'b0111;seg_led<=7'b0000010;end //state<=4'd7;end //6
4'd7: begin led<=4'b1011;seg_led<=7'b1101100;end //state<=4'd8;end //7
4'd8: begin led<=4'b1101;seg_led<=7'b0000000;end //state<=4'd9;end //8
4'd9: begin led<=4'b1110;seg_led<=7'b1000000;end //state<=4'd0;end //9
endcase
end
end
endmodule
FBGA{:smile:} Puppey 发表于 2015-1-1 11:16
FBGA
哈哈，新手到名字都搞错，呵呵，不好意思哈！ 按键消抖，自己查吧。
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