quartus II 10 SOPC加入DDR SDRAM时出错：Error: Following DDIO Output nod...
quartus II 10 SOPC加入DDR SDRAM时出错：Error: Following DDIO Output nodes could not be placed by the Fitter有大侠遇到过么？
DDR SDRAM模块是SOPC builder --> Memories and memory controllers --> SDRAM
跪求大师指点迷津！
你好，现在ALtera发布带有arm核的HPS的FGPA了，现在都在QSYS中做系统的互联了，我也想在这里提出一个问题，就是我想在QSYS中使用一个DDR3的控制器，界面中有一些参数需要设置，你研究过吗？ I face this problem before. You have to do some setting because there is too much bidir pins for 1 Vref.
1st :
Assigment-Device-Device and Pins option-Dual purpose pins(set all value to: use as regular I/O accept for DClock&nCEO.
2nd :
Assigment-Assigment Editor- Change all DQ,DQS and DM pins to (Output Enable Group). For the Value column, set any number same for those pins.
eg: DQ->Output Enable Group->123456(Value)
3rd :
Assigment-Pins(Change IO standard for all DDR related pins to SSTL-2 Class I.)
You now are able to compile without any fail hopefully. I face this before and want to help you.
Thank you:
Shahril
页:
[1]