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发表于 2014-7-18 17:53:20
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I face this problem before. You have to do some setting because there is too much bidir pins for 1 Vref.
1st :
Assigment-Device-Device and Pins option-Dual purpose pins(set all value to: use as regular I/O accept for DClock&nCEO.
2nd :
Assigment-Assigment Editor- Change all DQ,DQS and DM pins to (Output Enable Group). For the Value column, set any number same for those pins.
eg: DQ[0]->Output Enable Group->123456(Value)
3rd :
Assigment-Pins(Change IO standard for all DDR related pins to SSTL-2 Class I.)
You now are able to compile without any fail hopefully. I face this before and want to help you.
Thank you:
Shahril |
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