为什么Verilog任务模块在modelsim测试中输出是未知值？？
我在modelsim中写入如下Verilog代码：module task_alu;
integer num,sum,diff,prod,quot,int;
initial begin
num = 1;sum = 0;int = 1; //初始值
alu(num,sum,diff,prod,quot,int);
num = 2;
alu(num,sum,diff,prod,quot,int);
num = 4;
alu(num,sum,diff,prod,quot,int);
num = 8;
alu(num,sum,diff,prod,quot,int);
end
task alu;
input num;
output sum,diff,prod,quot,int;
integer num,sum,diff,prod,quot,int;
begin
sum = sum + int;
diff = int - sum;
prod = sum * int;
quot = prod / sum;
int = int + num;
$display("sum = %d,diff = %d,prod = %d,quot = %d,int = %d",sum,diff,prod,quot,int);
end
endtask
endmodule
仿真结果如下截图：
希望大神帮忙解决。。 怎么没人指点一下啊~~{:cry:}
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