|
我在modelsim中写入如下Verilog代码:
module task_alu;
integer num,sum,diff,prod,quot,int;
initial begin
num = 1;sum = 0;int = 1; //初始值
alu(num,sum,diff,prod,quot,int);
num = 2;
alu(num,sum,diff,prod,quot,int);
num = 4;
alu(num,sum,diff,prod,quot,int);
num = 8;
alu(num,sum,diff,prod,quot,int);
end
task alu;
input num;
output sum,diff,prod,quot,int;
integer num,sum,diff,prod,quot,int;
begin
sum = sum + int;
diff = int - sum;
prod = sum * int;
quot = prod / sum;
int = int + num;
$display("sum = %d,diff = %d,prod = %d,quot = %d,int = %d",sum,diff,prod,quot,int);
end
endtask
endmodule
仿真结果如下截图:
希望大神帮忙解决。。 |
本帖子中包含更多资源
您需要 登录 才可以下载或查看,没有帐号?注册
x
阿莫论坛20周年了!感谢大家的支持与爱护!!
曾经有一段真挚的爱情摆在我的面前,我没有珍惜,现在想起来,还好我没有珍惜……
|