产生50mv的梯形波，结果这样 (amobbs.com 阿莫电子技术论坛) -

mayo20102012 发表于 2014-4-13 13:40:28

产生50mv的梯形波，结果这样

产生50mv的梯形波，为什么会出现如图的波形，该要怎么滤波？

tam2907 发表于 2014-4-13 15:02:08

电路图？

lans0625 发表于 2014-4-13 16:27:50

上代码看看。。。。

mayo20102012 发表于 2014-4-13 18:11:25

lans0625 发表于 2014-4-13 16:27
上代码看看。。。。

是用verilog写的，产生2.5V的不错。50MV的不行，，估计50mv的干扰大过我要输出的，上代码了。。

//2.5V/7.5ms
//50mv/0.2ms
module Tra(CLK,RST_N,DA_SCLK1,DA_DIN1,DA_DIN2,DA_SYNC1,DA_SYNC2,DA_SCLK2,DA_data2);
input CLK;
input RST_N;
outputDA_SCLK1;
outputDA_SCLK2;
outputDA_DIN1;
outputDA_SYNC1;
outputDA_DIN2;
outputDA_SYNC2;
wire DA_WCLK;
//...........
//output DA_data1;
output DA_data2;

pll pll_inst(
            .inclk0(CLK),
            .c0(DA_SCLK1),
            .c1(DA_SCLK2),
            .c2(DA_WCLK)
            );

reg sync_cnt1;
reg    DA_SYNC1_r;
always @(posedge DA_WCLK or negedge RST_N)
begin
if(!RST_N)
sync_cnt1 <= 5'd0;
else if(sync_cnt1==5'd23)
sync_cnt1 <= 5'd0;
else
sync_cnt1 <= sync_cnt1 + 1'b1;
end
always @(posedge DA_WCLK or negedge RST_N)
begin
if(!RST_N)
DA_SYNC1_r <= 1'b0;
else if(sync_cnt1 < 5'd1)
DA_SYNC1_r <= 1'b1;
else
DA_SYNC1_r <= 1'b0;
end
assignDA_SYNC1 = DA_SYNC1_r;
regadr_en;
always @(posedge DA_WCLK or negedge RST_N)
begin
if(!RST_N)
adr_en <= 1'b0;
else if(sync_cnt1==5'd20)
adr_en <= 1'b1;
else
adr_en <= 1'b0;
end

wire adr_rom;
reg adr_rom_r;
wire DA_data1;
wire    rom_clk;
assign rom_clk = ~DA_WCLK;
assign adr_rom = adr_rom_r;
reg out_st;
reg high_cnt;
always @(posedge DA_WCLK or negedge RST_N)
begin
if(!RST_N)
begin
adr_rom_r <= 12'd0;
out_st <= 2'b00;
high_cnt <= 16'd0;
end
else
case(out_st)
   2'b00:begin
            if(adr_en && adr_rom_r<12'd3013 )
               adr_rom_r <= adr_rom_r + 1'b1;
            else if(adr_rom_r==12'd3013)
            begin

               out_st <= 2'b01;
            end
            else
               adr_rom_r <= adr_rom_r;
         end
   2'b01:begin
            adr_rom_r <= 12'd3013;
            if(high_cnt==16'd59999)
            begin
               out_st <= 2'b10;
               high_cnt <= 16'd0;
            end
            else
            begin
               high_cnt <= high_cnt + 1'b1;
               out_st <= 2'b01;
            end
         end
   2'b10:begin
            if(adr_en && adr_rom_r>12'd0 )
               adr_rom_r <= adr_rom_r - 1'b1;
            else if(adr_rom_r==12'd0)
            begin
               out_st <= 2'b11;
            end
            else
               adr_rom_r <= adr_rom_r;
         end
      2'b11:begin
            adr_rom_r <= 12'd0;
            if(high_cnt==16'd59999)
            begin
               out_st <= 2'b00;
               high_cnt <= 16'd0;
            end
            else
            begin
               high_cnt <= high_cnt + 1'b1;
               out_st <= 2'b11;
            end
         end
      default: out_st <= 2'b00;
      endcase
end
rom1 rom1_inst(
            .address(adr_rom),
            .clock(rom_clk),
            .q(DA_data1)
            );
regDA_DIN1_r;
reg st;
always @(posedge DA_WCLK or negedge RST_N)
begin
if(!RST_N)
begin
   DA_DIN1_r <= 1'b0;
   st <= 5'd0;
end
else
begin
   case(st)
      5'd0:begin
            if(DA_SYNC1_r==1'b1)
               begin
                  DA_DIN1_r <= 1'b0;//16
                  st<= 5'd1;
               end
               else
                  st <= 5'd0;
            end
      5'd1:begin DA_DIN1_r <= 1'b0; st <= 5'd2;end//15
      5'd2:begin DA_DIN1_r <= 1'b0; st <= 5'd3;end//14
      5'd3:begin DA_DIN1_r <= 1'b0; st <= 5'd4;end//13
      5'd4:begin DA_DIN1_r <= DA_data1; st <= 5'd5;end//12
      5'd5:begin DA_DIN1_r <= DA_data1; st <= 5'd6;end//11
      5'd6:begin DA_DIN1_r <= DA_data1; st <= 5'd7;end//10
      5'd7:begin DA_DIN1_r <= DA_data1; st <= 5'd8;end//9
      5'd8:begin DA_DIN1_r <= DA_data1; st <= 5'd9;end//8
      5'd9:begin DA_DIN1_r <= DA_data1; st <= 5'd10;end//7
      5'd10:begin DA_DIN1_r <= DA_data1; st <= 5'd11;end//6
      5'd11:begin DA_DIN1_r <= DA_data1; st <= 5'd12;end//5
      5'd12:begin DA_DIN1_r <= DA_data1; st <= 5'd13;end//4
      5'd13:begin DA_DIN1_r <= DA_data1; st <= 5'd14;end//3
      5'd14:begin DA_DIN1_r <= DA_data1; st <= 5'd15;end//2
      5'd15:begin DA_DIN1_r <= DA_data1; st <= 5'd0;end//1
      default st <= 5'd0;
      endcase
end
end
assignDA_DIN1 = DA_DIN1_r;
//.............50mv.................
//..................................
reg sync_cnt2;
reg    DA_SYNC2_r;
always @(posedge DA_WCLK or negedge RST_N)
begin
if(!RST_N)
sync_cnt2 <= 6'd0;
else if(sync_cnt2==6'd33)
sync_cnt2 <= 6'd0;
else
sync_cnt2 <= sync_cnt2 + 1'b1;
end
always @(posedge DA_WCLK or negedge RST_N)
begin
if(!RST_N)
DA_SYNC2_r <= 1'b0;
else if(sync_cnt2 < 6'd1)
DA_SYNC2_r <= 1'b1;
else
DA_SYNC2_r <= 1'b0;
end
assignDA_SYNC2 = DA_SYNC2_r;
regadr_en2;
always @(posedge DA_WCLK or negedge RST_N)
begin
if(!RST_N)
adr_en2 <= 1'b0;
else if(sync_cnt2==6'd20)
adr_en2 <= 1'b1;
else
adr_en2 <= 1'b0;
end
wire adr_rom2;
reg adr_rom_r2;
//wire DA_data2;

reg out_st2;
reg high_cnt2;
always @(posedge DA_WCLK or negedge RST_N)
begin
if(!RST_N)
begin
adr_rom_r2 <= 6'd0;
out_st2 <= 2'b00;
high_cnt2 <= 16'd0;
end
else
case(out_st2)
   2'b00:begin
            if(adr_en2 && adr_rom_r2<6'd59 )
               adr_rom_r2 <= adr_rom_r2 + 1'b1;
            else if(adr_rom_r==6'd59)
            begin

               out_st2 <= 2'b01;
            end
            else
               adr_rom_r2 <= adr_rom_r2;
         end
   2'b01:begin
            adr_rom_r2 <= 6'd59;
            if(high_cnt2==16'd59999)
            begin
               out_st2 <= 2'b10;
               high_cnt2 <= 16'd0;
            end
            else
            begin
               high_cnt2 <= high_cnt2 + 1'b1;
               out_st2 <= 2'b01;
            end
         end
   2'b10:begin
            if(adr_en2 && adr_rom_r>6'd0 )
               adr_rom_r2 <= adr_rom_r2 - 1'b1;
            else if(adr_rom_r==6'd0)
            begin
               out_st2 <= 2'b11;
            end
            else
               adr_rom_r2 <= adr_rom_r2;
         end
      2'b11:begin
            adr_rom_r2 <= 6'd0;
            if(high_cnt2==16'd59999)
            begin
               out_st2 <= 2'b00;
               high_cnt2 <= 16'd0;
            end
            else
            begin
               high_cnt2 <= high_cnt2 + 1'b1;
               out_st2 <= 2'b11;
            end
         end
      default: out_st2 <= 2'b00;
      endcase
end
assign adr_rom2 = adr_rom_r2;
rom3 rom3_inst(
            .address(adr_rom2),
            .clock(rom_clk),
            .q(DA_data2)
            );
regDA_DIN2_r;
reg st2;
always @(posedge DA_WCLK or negedge RST_N)
begin
if(!RST_N)
begin
   DA_DIN2_r <= 1'b0;
   st2 <= 5'd0;
end
else
begin
   case(st2)
      5'd0:begin
            if(DA_SYNC2_r==1'b1)
               begin
                  DA_DIN2_r <= 1'b0;//16
                  st2<= 5'd1;
               end
               else
                  st2 <= 5'd0;
            end
      5'd1:begin DA_DIN2_r <= 1'b0; st2 <= 5'd2;end//15
      5'd2:begin DA_DIN2_r <= 1'b0; st2 <= 5'd3;end//14
      5'd3:begin DA_DIN2_r <= 1'b0; st2 <= 5'd4;end//13
      5'd4:begin DA_DIN2_r <= 1'b0; st2 <= 5'd5;end//12
      5'd5:begin DA_DIN2_r <= 1'b0; st2 <= 5'd6;end//11
      5'd6:begin DA_DIN2_r <= 1'b0; st2 <= 5'd7;end//10
      5'd7:begin DA_DIN2_r <= 1'b0; st2 <= 5'd8;end//9
      5'd8:begin DA_DIN2_r <= 1'b0; st2 <= 5'd9;end//8
      5'd9:begin DA_DIN2_r <= 1'b0; st2 <= 5'd10;end//7
      5'd10:begin DA_DIN2_r <= DA_data2; st2 <= 5'd11;end//6
      5'd11:begin DA_DIN2_r <= DA_data2; st2 <= 5'd12;end//5
      5'd12:begin DA_DIN2_r <= DA_data2; st2 <= 5'd13;end//4
      5'd13:begin DA_DIN2_r <= DA_data2; st2 <= 5'd14;end//3
      5'd14:begin DA_DIN2_r <= DA_data2; st2 <= 5'd15;end//2
      5'd15:begin DA_DIN2_r <= DA_data2; st2 <= 5'd0;end//1
      default st2 <= 5'd0;
      endcase
end
end
assignDA_DIN2 = DA_DIN2_r;
endmodule

mayo20102012 发表于 2014-4-13 18:13:05

tam2907 发表于 2014-4-13 15:02
电路图？

额没啥电路图其实就一个DA，加了个RC滤波，悲催的是RC滤波还不管用，难道是R和C参数选取问题，我的截止频率已经很低了。。

mayo20102012 发表于 2014-4-13 18:16:53

lans0625 发表于 2014-4-13 16:27
上代码看看。。。。

2.5V和50MV的代码几乎一样，没怎么改，应该不是程序问题。。附上2。5V的波形，，模拟电路好长时间没碰了，多数忘了。。

爺@龙行天下 发表于 2014-4-13 21:03:45

好一个梯形波

sjx000000 发表于 2014-4-15 08:49:25

2.5V的波形很好。50mv 可能是干扰太大

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产生50mv的梯形波，结果这样