fpga4fun uart 代码仿真 求解
fpga4fun 是一个很不错的关于FPGA 的外国网站 里面提供了很多实例，不过最近好像登录不上了！其中有一个关于 uart 的实例很经典，当中关于波特率的一段尤其经典，可以不是很懂。
所以今天想仿真一下 ，看看这段经典代码的是如何实现的.....可惜捣鼓了很久都没仿出波形来，求各为大牛帮帮忙看看什么原因~~~~
这是fpga4fun uart 接收 的代码
// RS-232 RX module
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006
module async_receiver(clk, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle);
input clk, RxD;
output RxD_data_ready;// onc clock pulse when RxD_data is valid
output RxD_data;
parameter ClkFrequency = 50000000; // 25MHz
parameter Baud = 9600;
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
//so that multiple characters can be treated as a "packet"
output RxD_endofpacket;// one clock pulse, when no more data is received (RxD_idle is going high)
output RxD_idle;// no data is being received
// Baud generator (we use 8 times oversampling)
parameter Baud8 = Baud*8;
parameter Baud8GeneratorAccWidth = 16;
wire Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);
reg Baud8GeneratorAcc;
always @(posedge clk) Baud8GeneratorAcc <= Baud8GeneratorAcc + Baud8GeneratorInc;
wire Baud8Tick = Baud8GeneratorAcc;
////////////////////////////
reg RxD_sync_inv;
always @(posedge clk) if(Baud8Tick) RxD_sync_inv <= {RxD_sync_inv, ~RxD};
// we invert RxD, so that the idle becomes "0", to prevent a phantom character to be received at startup
reg RxD_cnt_inv;
reg RxD_bit_inv;
always @(posedge clk)
if(Baud8Tick)
begin
if( RxD_sync_inv && RxD_cnt_inv!=2'b11) RxD_cnt_inv <= RxD_cnt_inv + 2'h1;
else
if(~RxD_sync_inv && RxD_cnt_inv!=2'b00) RxD_cnt_inv <= RxD_cnt_inv - 2'h1;
if(RxD_cnt_inv==2'b00) RxD_bit_inv <= 1'b0;
else
if(RxD_cnt_inv==2'b11) RxD_bit_inv <= 1'b1;
end
reg state;
reg bit_spacing;
// "next_bit" controls when the data sampling occurs
// depending on how noisy the RxD is, different values might work better
// with a clean connection, values from 8 to 11 work
wire next_bit = (bit_spacing==4'd10);
always @(posedge clk)
if(state==0)
bit_spacing <= 4'b0000;
else
if(Baud8Tick)
bit_spacing <= {bit_spacing + 4'b0001} | {bit_spacing, 3'b000};
always @(posedge clk)
if(Baud8Tick)
case(state)
4'b0000: if(RxD_bit_inv) state <= 4'b1000;// start bit found?
4'b1000: if(next_bit) state <= 4'b1001;// bit 0
4'b1001: if(next_bit) state <= 4'b1010;// bit 1
4'b1010: if(next_bit) state <= 4'b1011;// bit 2
4'b1011: if(next_bit) state <= 4'b1100;// bit 3
4'b1100: if(next_bit) state <= 4'b1101;// bit 4
4'b1101: if(next_bit) state <= 4'b1110;// bit 5
4'b1110: if(next_bit) state <= 4'b1111;// bit 6
4'b1111: if(next_bit) state <= 4'b0001;// bit 7
4'b0001: if(next_bit) state <= 4'b0000;// stop bit
default: state <= 4'b0000;
endcase
reg RxD_data;
always @(posedge clk)
if(Baud8Tick && next_bit && state) RxD_data <= {~RxD_bit_inv, RxD_data};
reg RxD_data_ready, RxD_data_error;
always @(posedge clk)
begin
RxD_data_ready <= (Baud8Tick && next_bit && state==4'b0001 && ~RxD_bit_inv);// ready only if the stop bit is received
RxD_data_error <= (Baud8Tick && next_bit && state==4'b0001 &&RxD_bit_inv);// error if the stop bit is not received
end
reg gap_count;
always @(posedge clk) if (state!=0) gap_count<=5'h00; else if(Baud8Tick & ~gap_count) gap_count <= gap_count + 5'h01;
assign RxD_idle = gap_count;
reg RxD_endofpacket; always @(posedge clk) RxD_endofpacket <= Baud8Tick & (gap_count==5'h0F);
endmodule
这是我写的仿真代码
`timescale 1ns / 1ps
module async_receiver_tb;
wireRxD_endofpacket ;
reg RxD ;
reg clk ;
wire RxD_idle ;
wireRxD_data ;
wireRxD_data_ready;
async_receiver
DUT(
.RxD_endofpacket (RxD_endofpacket ) ,
.RxD (RxD ) ,
.clk (clk ) ,
.RxD_idle (RxD_idle ) ,
.RxD_data (RxD_data ) ,
.RxD_data_ready (RxD_data_ready ) );
parameter CLOCK_20NS = 20;
initial begin
clk = 1'b0;
forever
# (CLOCK_20NS/2) clk = ~clk; // 20ns CLOCK
end
parameter BPS_9600 = 104140,
SEND_DATA = 8'b1000_0011;
integer i;
initial begin
RxD = 1'b1; //RESET rs232_rx
# BPS_9600 RxD = 1'b0; // transmit START bit
for (i=0;i<8;i=i+1) //transmit DATA byte
# BPS_9600 RxD = SEND_DATA;
# BPS_9600 RxD = 1'b0; // transmit STOP bit
# BPS_9600 RxD = 1'b1; // bus IDLE
end
endmodule
运行仿真后总是没办法 出现波形~~~~
只要修改 reg Baud8GeneratorAcc; 对它赋个初始值就OK了。
但是仿真出来的结果还是有点奇怪， baudtick居然是两个clk 想不明白~~~~ 同求解释 xmu234 发表于 2014-1-9 13:01
同求解释
这个好久没去研究了，后来重新写了个testbench 又OK了！
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