FPGA做AD采样时,如何看AD芯片的时序图?
AD芯片的时序图提供的时间参数很多,比如转换时间、延时时间、各种最大、最小时间间隔等等,要用verilog来实现AD采样,应该关注AD芯片的哪些参数比较呢?难道所有的时间参数都需要去管? 都要考虑的 ,当然根据具体需求 ,有的可以不管 我用fpga采样的ADCS7476,SPI的,没有考虑那些东西 流氓马 发表于 2013-7-21 15:27 static/image/common/back.gif
我用fpga采样的ADCS7476,SPI的,没有考虑那些东西
你考虑了哪几个时间参数呢? 一个都没考虑,选型的时候,只考虑了速度,精度,通信方式,电压 流氓马 发表于 2013-7-21 16:16 static/image/common/back.gif
一个都没考虑,选型的时候,只考虑了速度,精度,通信方式,电压
你用的SPI接口是自己写的还是直接用的SPI核? //
// File: adc_driver.v
// Date: 07-Nov-05
// Author: I. Chuang <ichuang@mit.edu>
//
// Sample code for the MIT 6.111 labkit, demonstrating FPGA control of an
// analog to digital converter (National Semiconductor ADCS7476).
//
// This specific demo is made to drive the Digilent ADC peripheral module,
// which has two ADCS7476 chips.See http://www.digilentinc.com
//
// These ADC chips can be clocked up to 20 Mhz, and produce data serially.
// The maximum conversion rate is 1 megasamples per second.The input
// voltage should be between 0 and 3.3V.
//
// The four signals which interface to the Digilent module are:
//
// CS= chip select (negative logic)
// CLK = serial clock
// D0= serial data for first ADC
// D1= serial data for second ADC
module aa(clk,adc_cs_b,adc_clk,adc_data0,adc_data1,v0,v1,rdy,sss,ccs);
input clk;//晶振时钟50M
output adc_cs_b;
output adc_clk;
input adc_data0;
input adc_data1;
output sss,ccs;
output v0,v1; // ADC results - voltages (12 bits)
output rdy; // high for one clk cycle on conversion finish
// drive the digilent ADC board, doing continuous conversions
// rdy goes high for one clk cycle for each new conversion
//
// we use a counter to clock out the bits
// note that the ADCS7476 serial data is valid on falling edges
// of the adc clock.
reg count;
wire adc_cs_b = count<32 ? 0 : 1;
wire ccs = count<32 ? 0 : 1;
wire adc_clk = count;
wire sss = count;
wire rdy = count==32 ? 1 : 0;
wire adc_clk2 = adc_clk;
reg tmp0, tmp1;
reg v0,v1;
reg delay;
always @(posedge clk)
begin
delay <= (delay == 0) ? 0 : delay + 1;
if(delay==0) begin
count <= count==42 ? 0 : count + 1;
tmp0 <= (~adc_clk|adc_cs_b) ? tmp0 : {tmp0,adc_data0};
tmp1 <= (~adc_clk|adc_cs_b) ? tmp1 : {tmp1,adc_data1};
v0 <= rdy ? tmp0 : v0;
v1 <= rdy ? tmp1 : v1;
end
end
endmodule // adc_driver网上下的,我自己稍微改了一点点
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