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发表于 2013-7-21 16:27:27
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- //
- // File: adc_driver.v
- // Date: 07-Nov-05
- // Author: I. Chuang <ichuang@mit.edu>
- //
- // Sample code for the MIT 6.111 labkit, demonstrating FPGA control of an
- // analog to digital converter (National Semiconductor ADCS7476).
- //
- // This specific demo is made to drive the Digilent ADC peripheral module,
- // which has two ADCS7476 chips. See http://www.digilentinc.com
- //
- // These ADC chips can be clocked up to 20 Mhz, and produce data serially.
- // The maximum conversion rate is 1 megasamples per second. The input
- // voltage should be between 0 and 3.3V.
- //
- // The four signals which interface to the Digilent module are:
- //
- // CS = chip select (negative logic)
- // CLK = serial clock
- // D0 = serial data for first ADC
- // D1 = serial data for second ADC
- module aa(clk,adc_cs_b,adc_clk,adc_data0,adc_data1,v0,v1,rdy,sss,ccs);
- input clk;//晶振时钟50M
- output adc_cs_b;
- output adc_clk;
- input adc_data0;
- input adc_data1;
- output sss,ccs;
- output [11:0] v0,v1; // ADC results - voltages (12 bits)
- output rdy; // high for one clk cycle on conversion finish
-
- // drive the digilent ADC board, doing continuous conversions
- // rdy goes high for one clk cycle for each new conversion
- //
- // we use a counter to clock out the bits
- // note that the ADCS7476 serial data is valid on falling edges
- // of the adc clock.
- reg [6:0] count;
- wire adc_cs_b = count<32 ? 0 : 1;
- wire ccs = count<32 ? 0 : 1;
- wire adc_clk = count[0];
- wire sss = count[0];
- wire rdy = count==32 ? 1 : 0;
- wire adc_clk2 = adc_clk;
- reg [11:0] tmp0, tmp1;
- reg [11:0] v0,v1;
- reg [31:0] delay;
-
- always @(posedge clk)
- begin
- delay <= (delay == 0) ? 0 : delay + 1;
- if(delay==0) begin
- count <= count==42 ? 0 : count + 1;
- tmp0 <= (~adc_clk|adc_cs_b) ? tmp0 : {tmp0[10:0],adc_data0};
- tmp1 <= (~adc_clk|adc_cs_b) ? tmp1 : {tmp1[10:0],adc_data1};
- v0 <= rdy ? tmp0 : v0;
- v1 <= rdy ? tmp1 : v1;
- end
- end
- endmodule // adc_driver
复制代码 网上下的,我自己稍微改了一点点 |
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