应如何计算fifo中的wrusedw
module EASY_FIFO(
aclr,
Wr_Clk,
nWr,
Din,
Rd_Clk,
nRd,
Dout,
wrusedw
);
inputaclr,Wr_Clk, nWr, Rd_Clk, nRd;
input Din;
output Dout;
output wrusedw ;
reg Buff ;
reg Wr_Addr, Rd_Addr,wruser;
assign Dout = Buff;
assign wrusedw = Wr_Addr-Rd_Addr;//?????这里的计算有问题,没想明白如何处理
always @ (posedge Wr_Clk)
begin
if (~nWr )
Buff <= Din;
else
Buff <= Buff;
end
always @ (posedge Wr_Clk or negedge aclr)
if(!aclr) Wr_Addr<= 4'd0;
else if(~nWr)Wr_Addr <= Wr_Addr + 1'b1;
else Wr_Addr<= Wr_Addr;
always @ (posedge Rd_Clk or negedge aclr)
if(!aclr) Rd_Addr <= 4'd0;
else if(~nRd)Rd_Addr <= Rd_Addr + 1'b1;
else Rd_Addr <= Rd_Addr;
endmodule
reg Buff ;
reg Wr_Addr, Rd_Addr,wruser;
assign Dout = Buff;
assign wrusedw = Wr_Addr-Rd_Addr;//?????这里的计算有问题,没想明白如何处理
地址线用3位就没问题,无符号数减法。 高手谢谢分享
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