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module EASY_FIFO
(
aclr,
Wr_Clk,
nWr,
Din,
Rd_Clk,
nRd,
Dout,
wrusedw
);
input aclr,Wr_Clk, nWr, Rd_Clk, nRd;
input [15:0] Din;
output [15:0] Dout;
output [3:0] wrusedw ;
reg [15:0] Buff [7:0];
reg [3:0] Wr_Addr, Rd_Addr,wruser;
assign Dout = Buff[Rd_Addr];
assign wrusedw = Wr_Addr-Rd_Addr;//?????这里的计算有问题,没想明白如何处理
always @ (posedge Wr_Clk)
begin
if (~nWr )
Buff[Wr_Addr] <= Din;
else
Buff[Wr_Addr] <= Buff[Wr_Addr];
end
always @ (posedge Wr_Clk or negedge aclr)
if(!aclr) Wr_Addr<= 4'd0;
else if(~nWr)Wr_Addr <= Wr_Addr + 1'b1;
else Wr_Addr<= Wr_Addr;
always @ (posedge Rd_Clk or negedge aclr)
if(!aclr) Rd_Addr <= 4'd0;
else if(~nRd)Rd_Addr <= Rd_Addr + 1'b1;
else Rd_Addr <= Rd_Addr;
endmodule
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阿莫论坛20周年了!感谢大家的支持与爱护!!
知道什么是神吗?其实神本来也是人,只不过神做了人做不到的事情 所以才成了神。 (头文字D, 杜汶泽)
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