请教下，这是一个关于密码设置和读取比较的模块
LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;
ENTITY chucun IS
PORT(s0,s1,s2:IN std_logic; b1,b2,b3,b4:IN std_logic;
wr,rd:IN std_logic; f1,f2,f3,f4:OUT std_logic);
END chucun;
ARCHITECTURE F OF chucun IS
SIGNAL e11,e12,e13,e14:std_logic;
SIGNAL e21,e22,e23,e24:std_logic;
SIGNAL e31,e32,e33,e34:std_logic;
SIGNAL e41,e42,e43,e44:std_logic;
SIGNAL e51,e52,e53,e54:std_logic;
SIGNAL e61,e62,e63,e64:std_logic;
SIGNAL e71,e72,e73,e74:std_logic;
SIGNAL mid:std_logic_vector(2 DOWNTO 0);
BEGIN
mid<=s2&s1&s0;
PROCESS(mid)
BEGIN
IF(wr='1')THEN --写信号有效，写入密码存储
IF(mid="000")THEN
e11<=b1;e12<=b2;e13<=b3;e14<=b4;
f1<=e11;f2<=e12;f3<=e13;f4<=e14;
IF(mid="001")THEN
e21<=b1;e22<=b2;e23<=b3;e24<=b4;
f1<=e21;f2<=e22;f3<=e23;f4<=e24;
IF(mid="010")THEN
e31<=b1;e32<=b2;e33<=b3;e34<=b4;
f1<=e31;f2<=e32;f3<=e33;f4<=e34;
IF(mid="011")THEN
e41<=b1;e42<=b2;e43<=b3;e44<=b4;
f1<=e41;f2<=e42;f3<=e33;f4<=e34;
IF(mid="100")THEN
e51<=b1;e52<=b2;e53<=b3;e54<=b4;
f1<=e51;f2<=e52;f3<=e53;f4<=e54;
IF(mid="101")THEN
e61<=b1;e62<=b2;e63<=b3;e64<=b4;
f1<=e61;f2<=e62;f3<=e63;f4<=e64;
ELSE
e71<=b1;e72<=b2;e73<=b3;e74<=b4;
f1<=e71;f2<=e72;f3<=e73;f4<=e74;
END IF;
ELSIF(rd='1')THEN --读信号有效，读出密码比较
IF(mid="000")THEN
f1<=e11;f2<=e12;f3<=e13;f4<=e14;
IF(mid="001")THEN
f1<=e21;f2<=e22;f3<=e23;f4<=e24;
IF(mid="010")THEN
f1<=e31;f2<=e32;f3<=e33;f4<=e34;
IF(mid="100")THEN
f1<=e41;f2<=e42;f3<=e43;f4<=e44;
IF(mid="101")THEN
f1<=e51;f2<=e52;f3<=e53;f4<=e54;
IF(mid="110")THEN
f1<=e61;f2<=e62;f3<=e63;f4<=e64;
ELSE
f1<=e71;f2<=e72;f3<=e73;f4<=e74;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END F;此程序有什么问题，我在仿真的时候。当写信号高电平，有效输出。但是当读信号有效时，输出一直处于低电平。也就是等于最后一段的程序貌似没起到作用。
另，我把WR=1和RD=1的语句 掉下顺序后仿真。。貌似都没效了这是为什么啊？？？
s0-s2 是计数器模块的，用于地址选择 IF用的有点多了吧 Dionysus 发表于 2013-4-7 14:55 static/image/common/back.gif
IF用的有点多了吧
{:cry:} 新手，完全不会。。就稍微看的点懂。。。
现在是为了做毕设。 HDL很多年没用过了，不知道说得对不对：
1. 第18行，PROCESS()里只需要mid？不要加wr/rd？（这个不确定）
2. wr=1时，IF () THEN你用了6个，但是END IF只有第42行，问题应该出在这里。你要把58行以后的END IF移5行放在42~43行之间。
sme 发表于 2013-4-7 16:06 static/image/common/back.gif
HDL很多年没用过了，不知道说得对不对：
1. 第18行，PROCESS()里只需要mid？不要加wr/rd？（这个不确定） ...
{:hug:} 我这就去试试。。谢谢 chaepon 发表于 2013-4-7 16:16 static/image/common/back.gif
我这就去试试。。谢谢
PROCESS(mid)
BEGIN
IF(wr='1')THEN --写信号有效，写入密码存储
IF(mid="000")THEN
e11<=b1;e12<=b2;e13<=b3;e14<=b4;
f1<=e11;f2<=e12;f3<=e13;f4<=e14;
ELSIF(mid="001")THEN
e21<=b1;e22<=b2;e23<=b3;e24<=b4;
f1<=e21;f2<=e22;f3<=e23;f4<=e24;
ELSIF(mid="010")THEN
e31<=b1;e32<=b2;e33<=b3;e34<=b4;
f1<=e31;f2<=e32;f3<=e33;f4<=e34;
ELSIF(mid="011")THEN
e41<=b1;e42<=b2;e43<=b3;e44<=b4;
f1<=e41;f2<=e42;f3<=e33;f4<=e34;
ELSIF(mid="100")THEN
e51<=b1;e52<=b2;e53<=b3;e54<=b4;
f1<=e51;f2<=e52;f3<=e53;f4<=e54;
ELSIF(mid="101")THEN
e61<=b1;e62<=b2;e63<=b3;e64<=b4;
f1<=e61;f2<=e62;f3<=e63;f4<=e64;
ELSE
e71<=b1;e72<=b2;e73<=b3;e74<=b4;
f1<=e71;f2<=e72;f3<=e73;f4<=e74;
END IF;
ELSIF(rd='1')THEN --读信号有效，读出密码比较
IF(mid="000")THEN
f1<=e11;f2<=e12;f3<=e13;f4<=e14;
ELSIF(mid="001")THEN
f1<=e21;f2<=e22;f3<=e23;f4<=e24;
ELSIF(mid="010")THEN
f1<=e31;f2<=e32;f3<=e33;f4<=e34;
ELSIF(mid="100")THEN
f1<=e41;f2<=e42;f3<=e43;f4<=e44;
ELSIF(mid="101")THEN
f1<=e51;f2<=e52;f3<=e53;f4<=e54;
ELSIF(mid="110")THEN
f1<=e61;f2<=e62;f3<=e63;f4<=e64;
ELSE
f1<=e71;f2<=e72;f3<=e73;f4<=e74;
END IF;
END IF;
END PROCESS;
前面看错了，可能这样改吧 sme 发表于 2013-4-7 16:40 static/image/common/back.gif
PROCESS(mid)
BEGIN
IF(wr='1')THEN --写信号有效，写入密码存储
你就把IF变成elsif？ chaepon 发表于 2013-4-7 18:19 static/image/common/back.gif
你就把IF变成elsif？
是的。你仿过没？
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