关于VHDL的延时问题,怎么在进程中执行延时呢?
程序如下,这样的话在num赋给n的时候,num也同时被置0吧?怎么延时执行f进程呢?想了好久,求解呀!!!g:PROCESS(en)
BEGIN
IF en'EVENT AND en='0'THEN
n0 <=num0;
n1 <=num1;
n2 <=num2;
n3 <=num3;
n4 <=num4;
n5 <=num5;
n6 <=num6;
n7 <=num7;
END IF;
END PROCESS;
f:PROCESS(wave,en)
BEGIN
IF en='0' THEN
num0<=0;
num1<=0;
num2<=0;
num3<=0;
num4<=0;
num5<=0;
num6<=0;
num7<=0;
END IF;
END PROCESS; 还是想不明白,望有人能指点一下 楼主,这样子行不?
signal a:std_logic:='0';
g:PROCESS(en)
BEGIN
IF en'EVENT AND en='0'THEN
n0 <=num0;
n1 <=num1;
n2 <=num2;
n3 <=num3;
n4 <=num4;
n5 <=num5;
n6 <=num6;
n7 <=num7;
a<='1';
END IF;
if a='1' then
a<='0';
end if;
END PROCESS;
f:PROCESS(wave,en)
BEGIN
IF en='0'and a='1' THEN
num0<=0;
num1<=0;
num2<=0;
num3<=0;
num4<=0;
num5<=0;
num6<=0;
num7<=0;
END IF;
END PROCESS;
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