用ModelSim仿真时遇到如下警告# WARNING: No extended dataflow License...
波形如图 testbanch如下LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY DFF1_vhd_tst IS
END DFF1_vhd_tst;
ARCHITECTURE DFF1_arch OF DFF1_vhd_tst IS
-- constants
-- signals
SIGNAL clk : STD_LOGIC;
SIGNAL clr : STD_LOGIC;
SIGNAL d : STD_LOGIC;
SIGNAL q : STD_LOGIC;
COMPONENT DFF1
PORT (
clk : IN STD_LOGIC;
clr : IN STD_LOGIC;
d : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
i1 : DFF1
PORT MAP (
-- list connections between master ports and signals
clk => clk,
clr => clr,
d => d,
q => q
);
init : PROCESS
-- variable declarations
BEGIN
clr <= '0';
wait for 10ns;
clr <= '1';
wait for 40ns;
clr <= '0';
wait for 40ns;
-- code that executes only once
WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
-- code executes for every event on sensitivity list
--WAIT;
END PROCESS always;
d_always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
d<='0';
wait for 50ns;
d<='1';
wait for 50ns;
-- code executes for every event on sensitivity list
--WAIT;
END PROCESS d_always;
END DFF1_arch; 顶层文件以原理图方式输入的，原理图如下，用Quartus自带的仿真可以成功，我用的Quartus ii 9.1，仿真用的ModelSim—Altera 6.5b。仿真VHDL写的顶层文件没遇到过这个问题 用晶振给bclk，50M的，用信号源给tclk，50K的，其余控制信号单片机给，用示波器看START输出一直是高电平，单片机可以读到result，但start接到单片机引脚上就读不到数了，求大神指点指点，菜鸟在此万分感谢
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