modelsim仿真时clk出现 Hiz，这是什么意思?（真相如图）
如题testbench文件如下：
`timescale 1 ns/ 1 ns
module BintoBCD_vlg_tst();
reg clk;
reg bin_in;
wire dec_out0;
wire dec_out1;
wire dec_out2;
/****************************/
BintoBCD i1
(
.clk( clk ),
.bin_in( bin_in ),
.dec_out0( dec_out0 ),
.dec_out1( dec_out1 ),
.dec_out2( dec_out2 )
);
/****************************/
initial
begin
clk = 0;
bin_in = 8'd125;
end
always #10 clk = ~clk;
endmodule 顶起来！ 高手在人间！{:shy:} 问题已解决~工程建的有问题，重新建工程就行了！ 附上算法，网上下的！
module BintoBCD
(
input clk,
input bin_in, //输入8bit Bin码
output regdec_out0 = 4'h0, //输出3bit BCD码
output regdec_out1 = 4'h0,
output regdec_out2 = 4'h0
);
/***********************************************/
wire c_in;
wire c_out;
regbin_sreg;
regbit_cnt = 4'h0;
regdec_sreg0 = 4'h0;
regdec_sreg1 = 4'h0;
regdec_sreg2 = 4'h0;
wire next_sreg0, next_sreg1, next_sreg2;
wire load = ~|bit_cnt; //读入二进制数据，准备转换
wire convert_ready = ( bit_cnt == 4'h9 ); //转换成功
wire convert_end = ( bit_cnt == 4'ha ); //完毕，重新开始
/***********************************************/
always @ ( posedge clk )
begin
if( convert_end )
bit_cnt <= 4'h0;
else
bit_cnt <= bit_cnt+4'h1;
end
/***********************************************/
always @ ( posedge clk )
begin
if( load )
bin_sreg <= bin_in;
else
bin_sreg <= { bin_sreg, 1'b0 };
end
/***********************************************/
assign c_in= bin_sreg;
assign c_in= ( dec_sreg0 >= 5 );
assign c_in= ( dec_sreg1 >= 5 );
assign c_out = c_in;
assign c_out = c_in;
assign c_out = ( dec_sreg2 >= 5 );
/******************确定移位输出******************/
assign next_sreg0 = c_out ? ( { dec_sreg0, c_in } + 4'h6 )
: ( { dec_sreg0, c_in } );
assign next_sreg1 = c_out ? ( { dec_sreg1, c_in } + 4'h6 )
: ( { dec_sreg1, c_in } );
assign next_sreg2 = c_out ? ( { dec_sreg2, c_in } + 4'h6 )
: ( { dec_sreg2, c_in } );
/*******************装入数据********************/
always @ (posedge clk )
if( load )
begin
dec_sreg0 <= 4'h0;
dec_sreg1 <= 4'h0;
dec_sreg2 <= 4'h0;
end
else
begin
dec_sreg0 <= next_sreg0;
dec_sreg1 <= next_sreg1;
dec_sreg2 <= next_sreg2;
end
/*********************数据输出******************/
always @ ( posedge clk )
if( convert_ready )
begin
dec_out0 <= dec_sreg0;
dec_out1 <= dec_sreg1;
dec_out2 <= dec_sreg2;
end
/***********************************************/
endmodule
页:
[1]