基于Xilinx的IP核设计FIR滤波器 习作 出错！！
朋友送了张XC3S100E开发板，想拿来做个FIR滤波器玩下，参考文库的做法却提示找不到IO。新学ISE，希望懂的朋友来指导下，附件已经上传
参考文章： http://wenku.baidu.com/view/6b32c1d4195f312b3169a535.html###
Regenerate Core - fir16: All required files are available.
Process "Regenerate Core" completed successfully
Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "C:/Documents and Settings/Administrator/My Documents/ISE/FIR/fir.xst" -ofn "C:/Documents and Settings/Administrator/My Documents/ISE/FIR/fir.syr"
Reading design: fir.prj
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "ipcore_dir/fir16.v" in library work
Compiling verilog file "fir.v" in library work
Module <fir16> compiled
Module <fir> compiled
No errors in compilation
Analysis of file <"fir.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
ERROR:HDLCompilers:91 - "fir.v" line 39 Module 'fir16' does not have a port named 's_axis_data_tready'
ERROR:HDLCompilers:91 - "fir.v" line 40 Module 'fir16' does not have a port named 's_axis_data_tvalid'
ERROR:HDLCompilers:91 - "fir.v" line 41 Module 'fir16' does not have a port named 'm_axis_data_tvalid'
ERROR:HDLCompilers:91 - "fir.v" line 42 Module 'fir16' does not have a port named 'aclk'
ERROR:HDLCompilers:91 - "fir.v" line 43 Module 'fir16' does not have a port named 'm_axis_data_tdata'
ERROR:HDLCompilers:91 - "fir.v" line 44 Module 'fir16' does not have a port named 's_axis_data_tdata'
-->
Total memory usage is 140856 kilobytes
Number of errors : 6 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesize - XST" failed 检查一下你生成ip时设置的信号名与例程是否一致 本帖最后由 90999 于 2012-7-29 15:26 编辑
zkf0100007 发表于 2012-7-29 11:22 static/image/common/back.gif
检查一下你生成ip时设置的信号名与例程是否一致
谢谢提醒。
上午我自己又重新写了FILER_TB，现在数值是出来了，但是值好象是错的（负），而且发现出错时候DIN没有正确输入值。
MARK!{:smile:}
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