基于Xilinx的IP核设计FIR滤波器 习作 出错！！

90999

朋友送了张XC3S100E开发板，想拿来做个FIR滤波器玩下，参考文库的做法却提示找不到IO。

新学ISE，希望懂的朋友来指导下，附件已经上传

参考文章： http://wenku.baidu.com/view/6b32c1d4195f312b3169a535.html###

1. 
   
2. Regenerate Core - fir16: All required files are available.
   
3. 
   
4. Process "Regenerate Core" completed successfully
   
5. 
   
6. Started : "Synthesize - XST".
   
7. Running xst...
   
8. Command Line: xst -intstyle ise -ifn "C:/Documents and Settings/Administrator/My Documents/ISE/FIR/fir.xst" -ofn "C:/Documents and Settings/Administrator/My Documents/ISE/FIR/fir.syr"
   
9. Reading design: fir.prj
   
10. 
    
11. =========================================================================
    
12. *                          HDL Compilation                              *
    
13. =========================================================================
    
14. Compiling verilog file "ipcore_dir/fir16.v" in library work
    
15. Compiling verilog file "fir.v" in library work
    
16. Module <fir16> compiled
    
17. Module <fir> compiled
    
18. No errors in compilation
    
19. Analysis of file <"fir.prj"> succeeded.
    
20. 
    
21. 
    
22. =========================================================================
    
23. *                     Design Hierarchy Analysis                         *
    
24. =========================================================================
    
25. ERROR:HDLCompilers:91 - "fir.v" line 39 Module 'fir16' does not have a port named 's_axis_data_tready'
    
26. ERROR:HDLCompilers:91 - "fir.v" line 40 Module 'fir16' does not have a port named 's_axis_data_tvalid'
    
27. ERROR:HDLCompilers:91 - "fir.v" line 41 Module 'fir16' does not have a port named 'm_axis_data_tvalid'
    
28. ERROR:HDLCompilers:91 - "fir.v" line 42 Module 'fir16' does not have a port named 'aclk'
    
29. ERROR:HDLCompilers:91 - "fir.v" line 43 Module 'fir16' does not have a port named 'm_axis_data_tdata'
    
30. ERROR:HDLCompilers:91 - "fir.v" line 44 Module 'fir16' does not have a port named 's_axis_data_tdata'
    
31. -->
    
32. 
    
33. Total memory usage is 140856 kilobytes
    
34. 
    
35. Number of errors   :    6 (   0 filtered)
    
36. Number of warnings :    0 (   0 filtered)
    
37. Number of infos    :    0 (   0 filtered)
    
38. 
    
39. 
    
40. Process "Synthesize - XST" failed

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zkf0100007

检查一下你生成ip时设置的信号名与例程是否一致

90999

zkf0100007 发表于 2012-7-29 11:22
检查一下你生成ip时设置的信号名与例程是否一致

谢谢提醒。
上午我自己又重新写了FILER_TB，现在数值是出来了，但是值好象是错的（负），而且发现出错时候DIN没有正确输入值。

飞鹤王子

MARK!