# Error loading design
在用modelsim仿真的时候出现# Error loading design
该如何解决，望各位给予关照，谢谢！
testbench:
`timescale 1ns/1ns
module counter4;
reg clk,reset;
wire out;
parameter DELAY = 100;
counter4 counter4(.clk(clk),.reset(reset),.out(out));
initial
begin
clk = 0;
reset = 1;
#DELAY reset=0;
#(DELAY * 20) $finish;
end
initial $monitor($time,,,"clk = %d reset = %d out = %d",clk,reset,out );
endmodule
报告结果：
# vsim work.counter4
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: F:/modelsim_workspace/counter4/rtl_2/counter4_tb.v(8): (vopt-2133) Instantiating 'counter4' has exceeded the recursion depth limit of 200.
# Optimization failed
# Error loading design 你的代码中有嵌套循环。
module counter4;
counter4 counter4(.clk(clk),.reset(reset),.out(out)); redcore 发表于 2012-2-5 16:56 static/image/common/back.gif
你的代码中有嵌套循环。
module counter4;
十分感谢！
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