【求教】用移位加3法实现二进制转BCD（VHDL）问题
程序如下请大家看看哪里有问题啊？LIBRARY IEEE;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY bintobcd IS
PORT ( clk : IN std_logic;
bin : IN std_logic_vector(9 downto 0);
bcd : OUT std_logic_vector(15 downto 0);
st : OUT std_logic_vector(1 downto 0));
END bintobcd;
ARCHITECTURE one of bintobcd is
SIGNAL btemp: std_logic_vector(15 downto 0);
SIGNAL b_mid: std_logic_vector(9 downto 0);
SIGNAL cnt : std_logic;
SIGNAL count: std_logic_vector(4 downto 0);
TYPE stateis (s0,s1,s2);
SIGNAL current_state,next_state : state;
BEGIN
reg:PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF cnt ='1' THEN
count <= count+1;
ELSE
count <= "00000";
END IF;
current_state <= next_state;
END IF;
END PROCESS;
com:PROCESS (current_state,count)
BEGIN
CASE current_state is
WHEN s0 => st <= "00";
cnt <= '0';
next_state <= s1;
WHEN s1 =>
st <= "01";
cnt<= '1';
next_state <= s2;
WHEN s2 =>
st <= "10";
cnt<= '1';
IF count <= "10100" THEN
next_state <= s1;
ELSE
next_state <= s0;
END IF;
WHEN OTHERS =>
next_state <= s0;
END CASE;
END PROCESS com;
output : PROCESS (current_state,bin,btemp,b_mid,count)
VARIABLE bt : std_logic_vector(15 downto 0);
BEGIN
CASEcurrent_state IS
WHEN s0 =>
bcd<=(OTHERS => '0');
btemp<=(OTHERS => '0');
b_mid <= bin;
WHEN s1 =>
bt := btemp(14 downto 0)&b_mid(9);
b_mid(9 downto 1)<= b_mid(8 downto 0)
WHEN s2 =>
IF bt(15 downto 12)>"0100" THEN
bt(15 downto 12):= bt(15 downto 12)+"0011";
ELSIF bt(11 downto 8)>"0100" THEN
bt(11 downto 8):= bt(11 downto 8)+"0011";
ELSIF bt(7 downto 4)>"0100" THEN
bt(7 downto 4):=bt(7 downto 4)+"0011";
ELSIF bt(3 downto 0)>"0100" THEN
bt(3 downto 0):=bt(3 downto 0)+"0011";
END IF;
bcd<=bt;
btemp<=bt;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output;
END one; 求高手点拨下啊。。。
页:
[1]