verilog的多个模块如何实现整体功能啊 新手 求帮助
我正学习FPGA，今天看到一个设计，他把设计分成4-led0,led1,led2,led3部分，还有个顶层部分-top模块,所有程序如下，那么各个模块是如何实现整体功能的啊？在用quartus写程序的时候要写下面那一部分啊，我就是想不明白，顶层部分干嘛啊？求大师指点module led0_module
(
CLK, RSTn, LED_Out
);
input CLK;
input RSTn;
output LED_Out;
/*************************************/
parameter T10MS = 21'd2_000_000;
/*************************************/
reg Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 21'd0;
else if( Count1 == T10MS )
Count1 <= 21'd0;
else
Count1 <= Count1 + 1'b1;
/*************************************/
reg rLED_Out;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rLED_Out <= 1'b0;
else if( Count1 >= 21'd0 && Count1 < 21'd500_000 )
rLED_Out <= 1'b1;
else
rLED_Out <= 1'b0;
/***************************************/
assign LED_Out = rLED_Out;
/***************************************/
endmodule
module led1_module
(
CLK, RSTn, LED_Out
);
input CLK;
input RSTn;
output LED_Out;
/*************************************/
parameter T10MS = 21'd2_000_000;
/*************************************/
reg Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 21'd0;
else if( Count1 == T10MS )
Count1 <= 21'd0;
else
Count1 <= Count1 + 1'b1;
/*************************************/
reg rLED_Out;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rLED_Out <= 1'b0;
else if( Count1 >= 21'd500_000 && Count1 < 21'd1_000_000 )
rLED_Out <= 1'b1;
else
rLED_Out <= 1'b0;
/***************************************/
assign LED_Out = rLED_Out;
/***************************************/
endmodule
module led2_module
(
CLK, RSTn, LED_Out
);
input CLK;
input RSTn;
output LED_Out;
/*************************************/
parameter T10MS = 21'd2_000_000;
/*************************************/
reg Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 21'd0;
else if( Count1 == T10MS )
Count1 <= 21'd0;
else
Count1 <= Count1 + 1'b1;
/*************************************/
reg rLED_Out;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rLED_Out <= 1'b0;
else if( Count1 >= 21'd1_000_000 && Count1 < 21'd1_500_000 )
rLED_Out <= 1'b1;
else
rLED_Out <= 1'b0;
/***************************************/
assign LED_Out = rLED_Out;
/***************************************/
endmodule
module top_module
(
CLK, RSTn, LED_Out
);
input CLK;
input RSTn;
output LED_Out;
/*******************************/
wire LED0_Out;
led0_module U1
(
.CLK( CLK ),
.RSTn( RSTn ),
.LED_Out( LED0_Out )
);
/*********************************/
wire LED1_Out;
led1_module U2
(
.CLK( CLK ),
.RSTn( RSTn ),
.LED_Out( LED1_Out )
);
/*********************************/
wire LED2_Out;
led2_module U3
(
.CLK( CLK ),
.RSTn( RSTn ),
.LED_Out( LED2_Out )
);
/*********************************/
wire LED3_Out;
led3_module U4
(
.CLK( CLK ),
.RSTn( RSTn ),
.LED_Out( LED3_Out )
);
/**********************************/
assign LED_Out = { LED3_Out, LED2_Out, LED1_Out, LED0_Out};
/***********************************/
endmodule 忘记把led3程序写上，但不影响我的疑问，望大师指点啊 将不同模块放在同一工程下
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