初学FPGA,困惑:加法器实现
现在有一个加法器模块,如下==============================================================================================================================================
module FullAdder(a, b, cin, sum, cout);
input a, b, cin;
output sum, cout;
assign {cout, sum} = a + b + cin;
endmodule
==============================================================================================================================================
现在想实现两个8位2进制数a_in、b_in,cin的加和,结果为result、cout。希望采用最省资源的方式实现:采用时序电路,实现每一对相应位的加和,而不增加硬件电路,这个该怎么做?
望各位前辈指教。谢谢! 各位前辈,在线等啊!! 自己写了一下代码:是错的,而且知道错误的原因,但如何修改呢?
========================================================================================================================
module ALU(clk, a, b, cin, result, cout);
inputa, b;
input cin;
input clk;
output result;
output cout;
wire carry0;
wire carry1;
reg counter;
// module 实例化
// 8-bit ripple adder
always @(posedge clk)begin
case (counter)
0: begin
FullAdder fa(a, b, cin, result, carry0);
counter<=counter+1;
end
1: begin
FullAdder fa(a, b, carry0, result, carry1);
counter<=counter+1;
end
2:begin
FullAdder fa(a, b, carry1, result, carry0);
counter<=counter+1;
end
3: begin
FullAdder fa(a, b, carry0, result, carry1);
counter<=counter+1;
end
4: begin
FullAdder fa(a, b, carry1, result, carry0);
counter<=counter+1;
end
5: begin
FullAdder fa(a, b, carry0, result, carry1);
counter<=counter+1;
end
6: begin
FullAdder fa(a, b, carry1, result, carry0);
counter<=counter+1;
end
7: begin
FullAdder fa(a, b, carry0, result, cout);
counter<=0;
end
default:
result=0;
endcase
end
endmodule
module FullAdder(a, b, cin, sum, cout);
input a, b, cin;
output sum, cout;
assign {cout, sum} = a + b + cin;
endmodule 虽然我不知道怎么改,但帮你顶一个 你8个实例怎么名字都一样? 应该是 FullAdder fa(a, b, carry5, result, carry6);才对吧 现在的综合器,都支持直接写加号。
“采用时序电路,实现每一对相应位的加和,而不增加硬件电路,这个该怎么做?”
加法器是综合逻辑,不用时钟,不算是时序电路吧。
module adder8(a, b, cin, sum, cout);
input a, b;
input cin;
output sum;
output cout;
assign {cout, sum} = a + b + {7'b0000000, cin};
endmodule
试试看这样行吗?
页:
[1]