请各位看看，我这段代码能否正确读写SSRAM
问题如题。//----------芯片使能-始终选中--------------------------//
assignoSRAM_CE1_N = 1'b0;
assignoSRAM_CE2 = 1'b1;
assignoSRAM_CE3_N = 1'b0;
//---------------OK------------------------------------//
//----------芯片的读写使能-----------------------------//
always@(iSW) begin
if (!iSW) begin //read;
oSRAM_GW_N <= 1'b1;
oSRAM_OE_N <= 1'b0;
oSRAM_WE_N <= 1'b1;
end
else begin //write;
oSRAM_GW_N <= 1'b0;
oSRAM_OE_N <= 1'b1;
oSRAM_WE_N <= 1'b0;
end
end
//----------------OK-----------------------------------//
//-----------SSRAM的读写控制---------------------------//
reg adr_w;
always@(posedge oCLK_40 or negedge iKEY) begin
if (!iKEY)
adr_w <= 16'b0;
else if (adr_w < 65535)
adr_w <=adr_w+16'b0000_0000_0000_0001;
else
adr_w <= adr_w;
end
reg reg_2;
always@(posedge oCLK_40 or negedge iKEY) begin
if (!iKEY) begin
;
end
else begin
if (iSW) begin //write;
oSRAM_A<= adr_w; //写地址信号
SRAM_DQ<= wire_2; //数据信号
end
else if(iSW==1'b0)begin
if (flag) begin //read;
oSRAM_A<= adr; //读地址信号
reg_2 <= SRAM_DQ;//数据信号
end
else begin
;
end
end
end
end
//----------------------OK-----------------------------//
读出数据的地址是adr，因为我读出的数据是要通过VGA在屏幕上显示出来的，所以读写不用同一个地址信号。
VGA那一块我测试过没有错误。
还请高手帮帮忙！ 回复【楼主位】lslong 大龙
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鉴于上面的可读性差，我把图片贴上了
http://cache.amobbs.com/bbs_upload782111/files_39/ourdev_641568SDMNA1.jpg
(原文件名:QQ截图未命名.jpg) 看程序是一个地址一个数，比较简单的操作，没用到burst。对照datasheet控制信号给对就可以了，另外注意读操作可能不是马上出数据，出数据要延迟几个clk 有没有 IS61VPS102418A 或 IS61LPS102418A 控制方式? 回复【3楼】d-link
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您是指ADVADSCADSP这几个管脚吗？我没有用突发的方式。 这段代码是否能用?好像寫入有問題{:curse:}
module sram_control (
iRST,
iCLK,
iCYC,
iADR,
iSEL,
iWE,
iDAT,
oDAT,
oACK,
SRAM_A,
SRAM_ADSCB,
SRAM_CS1B,
SRAM_OEB,
SRAM_WEB,
SRAM_DQ,
SRAM_CS2,
SRAM_ADVB,
SRAM_ADSPB,
SRAM_GWB,
SRAM_CS2B,
SRAM_WR_N
);
input iRST ;
input iCLK ;
input iCYC ;
input iADR ;
input [ 3:0] iSEL ;
input iWE;
input iDAT ;
output oDAT ;
outputoACK ;
//----------------------------------------------------
output SRAM_A; reg SRAM_A;
outputSRAM_ADSCB; reg SRAM_ADSCB;
outputSRAM_CS1B;reg SRAM_CS1B;
outputSRAM_OEB; wire SRAM_OEB;
outputSRAM_WEB; reg SRAM_WEB;
output SRAM_WR_N;
inout SRAM_DQ;
reg SRAM_D_O; // data to SSRAM
reg SRAM_D_T; // 0 for output
outputSRAM_CS2; wire SRAM_CS2 =1'b1;
outputSRAM_ADVB;wire SRAM_ADVB =1'b1;
outputSRAM_ADSPB; wire SRAM_ADSPB =1'b1;
outputSRAM_GWB; wire SRAM_GWB =1'b1;
outputSRAM_CS2B;wire SRAM_CS2B =1'b0;
/*********************************************************/
wire S_A;
wire S_ADSCB;
wire S_CS1B;
wire S_OEB;
wire S_WEB;
wire S_D_I =SRAM_DQ;
wire S_D_O;
wire S_D_T;
reg S_OEB_REG;
assignSRAM_OEB =S_OEB&S_OEB_REG;
always @ (posedge iCLK) begin
if (iRST==1'b1) begin
SRAM_A <= 19'h0;
SRAM_ADSCB <= 1'b1;
SRAM_CS1B<= 1'b1;
SRAM_WEB <= 4'hF;
SRAM_D_O <= 32'h0;
SRAM_D_T <= 1'b1;
S_OEB_REG<= 1'b1;
end else begin
SRAM_A <= S_A ;
SRAM_ADSCB <= S_ADSCB;
SRAM_CS1B<= S_CS1B ;
SRAM_WEB <= S_WEB;
SRAM_D_O <= S_D_O;
SRAM_D_T <= S_D_T;
S_OEB_REG<= S_OEB;
end
end
//----------------------------------------------------
sram_core U1 (
.iRST (iRST),
.iCLK (iCLK),
.iCYC (iCYC),
.iADR (iADR),
.iSEL (iSEL),
.iWE (iWE ),
.iDAT (iDAT),
.oDAT (oDAT),
.oACK (oACK),
.SRAM_A (S_A ),
.SRAM_ADSCB (S_ADSCB),
.SRAM_CS1B (S_CS1B ),
.SRAM_OEB (S_OEB ),
.SRAM_WEB (S_WEB ),
.SRAM_D_O (S_D_O ),
.SRAM_D_I (S_D_I ),
.SRAM_D_T (S_D_T )
);
assign SRAM_DQ = SRAM_D_T ? 32'hzzzzzzzz : SRAM_D_O;
assign SRAM_WR_N = SRAM_D_T;
endmodule
//--------------------------------------------------------------------------
module sram_core (
iRST,
iCLK,
iCYC,
iADR,
iSEL,
iWE,
iDAT,
oDAT,
oACK,
SRAM_A,
SRAM_ADSCB,
SRAM_CS1B,
SRAM_OEB,
SRAM_WEB,
SRAM_D_O,
SRAM_D_I,
SRAM_D_T
);
input iRST ;
input iCLK ;
input iCYC ;
input iADR ;
input [ 3:0] iSEL ;
input iWE;
input iDAT ;
output oDAT ;reg oDAT ;
outputoACK ;
//----------------------------------------------------
output SRAM_A; reg SRAM_A;
outputSRAM_ADSCB; reg SRAM_ADSCB;
outputSRAM_CS1B;reg SRAM_CS1B;
outputSRAM_OEB; reg SRAM_OEB;
outputSRAM_WEB; reg SRAM_WEB;
input SRAM_D_I; wire SRAM_D_I; // data from SSRAM
output SRAM_D_O; reg SRAM_D_O; // data to SSRAM
outputSRAM_D_T; reg SRAM_D_T; // 0 for output
/*********************************************************/
reg wb_ack_reg;
reg SRAM_OEB_0, SRAM_OEB_1, SRAM_OEB_2;
reg read_on;
assignoACK =(iWE) ? iCYC : wb_ack_reg;
always @ (posedge iCLK ) begin
if (iRST==1'b1) begin
oDAT <= 32'h0;
SRAM_A <= 20'h0;
SRAM_ADSCB <= 1'b1;
SRAM_CS1B<= 1'b1;
SRAM_WEB <= 4'hF;
SRAM_D_O <= 32'h0;
SRAM_D_T <= 1'b1;
wb_ack_reg <= 1'b0;
SRAM_OEB <= 1'b1;
SRAM_OEB_0 <= 1'b1;
SRAM_OEB_1 <= 1'b1;
read_on <= 1'b0;
end else begin
if (iCYC&~read_on) begin
SRAM_A <= iADR;
SRAM_ADSCB <= 1'b0;
SRAM_CS1B<= 1'b0;
SRAM_WEB <= (iWE) ? ~iSEL : 4'hF;
SRAM_D_O <= iDAT;
SRAM_D_T <= ~iWE;
SRAM_OEB_0 <= iWE;
end else begin
SRAM_A <= 20'h0;
SRAM_ADSCB <= 1'b1;
SRAM_CS1B<= 1'b1;
SRAM_WEB <= 4'hF;
SRAM_D_O <= 32'h0;
SRAM_D_T <= 1'b1;
SRAM_OEB_0 <= 1'b1;
end
SRAM_OEB_1 <= SRAM_OEB_0;
SRAM_OEB_2 <= SRAM_OEB_1;
SRAM_OEB <= SRAM_OEB_2;
if (SRAM_OEB==1'b0) begin
oDAT <= SRAM_D_I;
wb_ack_reg <= 1'b1;
end else begin
wb_ack_reg <= 1'b0;
end
if (iCYC&~iWE&~read_on) begin
read_on <= 1'b1;
end else begin
if (read_on&oACK) read_on <= 1'b0;
end
end
end
endmodule
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