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发表于 2012-9-7 11:35:39
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显示全部楼层
这段代码是否能用?好像寫入有問題
module sram_control (
iRST,
iCLK,
iCYC,
iADR,
iSEL,
iWE,
iDAT,
oDAT,
oACK,
SRAM_A,
SRAM_ADSCB,
SRAM_CS1B,
SRAM_OEB,
SRAM_WEB,
SRAM_DQ,
SRAM_CS2,
SRAM_ADVB,
SRAM_ADSPB,
SRAM_GWB,
SRAM_CS2B,
SRAM_WR_N
);
input iRST ;
input iCLK ;
input iCYC ;
input [31:0] iADR ;
input [ 3:0] iSEL ;
input iWE ;
input [31:0] iDAT ;
output [31:0] oDAT ;
output oACK ;
//----------------------------------------------------
output [18:0] SRAM_A; reg [18:0] SRAM_A;
output SRAM_ADSCB; reg SRAM_ADSCB;
output SRAM_CS1B; reg SRAM_CS1B;
output SRAM_OEB; wire SRAM_OEB;
output [3:0] SRAM_WEB; reg [3:0] SRAM_WEB;
output SRAM_WR_N;
inout [31:0] SRAM_DQ;
reg [31:0] SRAM_D_O; // data to SSRAM
reg SRAM_D_T; // 0 for output
output SRAM_CS2; wire SRAM_CS2 = 1'b1;
output SRAM_ADVB; wire SRAM_ADVB = 1'b1;
output SRAM_ADSPB; wire SRAM_ADSPB = 1'b1;
output SRAM_GWB; wire SRAM_GWB = 1'b1;
output SRAM_CS2B; wire SRAM_CS2B = 1'b0;
/*********************************************************/
wire [19:0] S_A;
wire S_ADSCB;
wire S_CS1B;
wire S_OEB;
wire [3:0] S_WEB;
wire [31:0] S_D_I = SRAM_DQ;
wire [31:0] S_D_O;
wire S_D_T;
reg S_OEB_REG;
assign SRAM_OEB = S_OEB&S_OEB_REG;
always @ (posedge iCLK) begin
if (iRST==1'b1) begin
SRAM_A <= 19'h0;
SRAM_ADSCB <= 1'b1;
SRAM_CS1B <= 1'b1;
SRAM_WEB <= 4'hF;
SRAM_D_O <= 32'h0;
SRAM_D_T <= 1'b1;
S_OEB_REG <= 1'b1;
end else begin
SRAM_A <= S_A[18:0] ;
SRAM_ADSCB <= S_ADSCB;
SRAM_CS1B <= S_CS1B ;
SRAM_WEB <= S_WEB ;
SRAM_D_O <= S_D_O ;
SRAM_D_T <= S_D_T ;
S_OEB_REG <= S_OEB;
end
end
//----------------------------------------------------
sram_core U1 (
.iRST (iRST ),
.iCLK (iCLK ),
.iCYC (iCYC ),
.iADR (iADR ),
.iSEL (iSEL ),
.iWE (iWE ),
.iDAT (iDAT ),
.oDAT (oDAT ),
.oACK (oACK ),
.SRAM_A (S_A ),
.SRAM_ADSCB (S_ADSCB ),
.SRAM_CS1B (S_CS1B ),
.SRAM_OEB (S_OEB ),
.SRAM_WEB (S_WEB ),
.SRAM_D_O (S_D_O ),
.SRAM_D_I (S_D_I ),
.SRAM_D_T (S_D_T )
);
assign SRAM_DQ = SRAM_D_T ? 32'hzzzzzzzz : SRAM_D_O;
assign SRAM_WR_N = SRAM_D_T;
endmodule
//--------------------------------------------------------------------------
module sram_core (
iRST,
iCLK,
iCYC,
iADR,
iSEL,
iWE,
iDAT,
oDAT,
oACK,
SRAM_A,
SRAM_ADSCB,
SRAM_CS1B,
SRAM_OEB,
SRAM_WEB,
SRAM_D_O,
SRAM_D_I,
SRAM_D_T
);
input iRST ;
input iCLK ;
input iCYC ;
input [31:0] iADR ;
input [ 3:0] iSEL ;
input iWE ;
input [31:0] iDAT ;
output [31:0] oDAT ; reg [31:0] oDAT ;
output oACK ;
//----------------------------------------------------
output [19:0] SRAM_A; reg [19:0] SRAM_A;
output SRAM_ADSCB; reg SRAM_ADSCB;
output SRAM_CS1B; reg SRAM_CS1B;
output SRAM_OEB; reg SRAM_OEB;
output [3:0] SRAM_WEB; reg [3:0] SRAM_WEB;
input [31:0] SRAM_D_I; wire [31:0] SRAM_D_I; // data from SSRAM
output [31:0] SRAM_D_O; reg [31:0] SRAM_D_O; // data to SSRAM
output SRAM_D_T; reg SRAM_D_T; // 0 for output
/*********************************************************/
reg wb_ack_reg;
reg SRAM_OEB_0, SRAM_OEB_1, SRAM_OEB_2;
reg read_on;
assign oACK = (iWE) ? iCYC : wb_ack_reg;
always @ (posedge iCLK ) begin
if (iRST==1'b1) begin
oDAT <= 32'h0;
SRAM_A <= 20'h0;
SRAM_ADSCB <= 1'b1;
SRAM_CS1B <= 1'b1;
SRAM_WEB <= 4'hF;
SRAM_D_O <= 32'h0;
SRAM_D_T <= 1'b1;
wb_ack_reg <= 1'b0;
SRAM_OEB <= 1'b1;
SRAM_OEB_0 <= 1'b1;
SRAM_OEB_1 <= 1'b1;
read_on <= 1'b0;
end else begin
if (iCYC&~read_on) begin
SRAM_A <= iADR[21:2];
SRAM_ADSCB <= 1'b0;
SRAM_CS1B <= 1'b0;
SRAM_WEB <= (iWE) ? ~iSEL : 4'hF;
SRAM_D_O <= iDAT;
SRAM_D_T <= ~iWE;
SRAM_OEB_0 <= iWE;
end else begin
SRAM_A <= 20'h0;
SRAM_ADSCB <= 1'b1;
SRAM_CS1B <= 1'b1;
SRAM_WEB <= 4'hF;
SRAM_D_O <= 32'h0;
SRAM_D_T <= 1'b1;
SRAM_OEB_0 <= 1'b1;
end
SRAM_OEB_1 <= SRAM_OEB_0;
SRAM_OEB_2 <= SRAM_OEB_1;
SRAM_OEB <= SRAM_OEB_2;
if (SRAM_OEB==1'b0) begin
oDAT <= SRAM_D_I;
wb_ack_reg <= 1'b1;
end else begin
wb_ack_reg <= 1'b0;
end
if (iCYC&~iWE&~read_on) begin
read_on <= 1'b1;
end else begin
if (read_on&oACK) read_on <= 1'b0;
end
end
end
endmodule |
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