这个20秒倒计时咋都这么难调试呢??
......signal reset_all,begin_all:std_logic;--复位信号,开始信号
--clk_1khz:时钟,reset_all:重置信号,begin_all;开始信号
process(clk_1hz,reset_all)
begin
if(clk_1hz'event and clk_1hz='1')then
if (reset_all='1') then time_2<="0000";time_1<="0010";
elsif(time_2="0000" and time_1="0000")then begin_all<=1;
elsif(time_2="0000")then time_2<="1001";time_1<=time_1-1;
else time_2<=time_2-1;
end if;
end if;
end if;
end if;
end process;
------------------------------------------------
无论咋改都是:
Error (10500): VHDL syntax error at Test.vhd(103) near text "if";expecting "process"
------------无语了,急死了快... 难道是逻辑错误?没有吧./emotion/em026.gif./emotion/em026.gif./emotion/em026.gif 多了两个endif
语法问题
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