vhdl的问题，请大神关注
本人写了一个抢答器的fpga程序，如下LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY qiangdaqi IS
PORT(K,S1,S2,S3,S4,S5,S6,S7:IN STD_LOGIC;
LED7S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END qiangdaqi;
ARCHITECTURE one OF qiangdaqi IS
SIGNAL ENA:STD_LOGIC;
SIGNAL Q:STD_LOGIC_VECTOR(7 DOWNTO 1);
BEGIN
ENA<=NOT(Q(7) OR Q(6) OR Q(5) OR Q(4) OR Q(3) OR Q(2) OR Q(1));
A_PRO:PROCESS(K,ENA)
BEGIN
IF K='0'THEN Q<="0000000";
ELSIF ENA='1' AND S1='1'THEN Q<="0000001";
ELSIF ENA='1' AND S2='1'THEN Q<="0000010";
ELSIF ENA='1' AND S3='1'THEN Q<="0000100";
ELSIF ENA='1' AND S4='1'THEN Q<="0001000";
ELSIF ENA='1' AND S5='1'THEN Q<="0010000";
ELSIF ENA='1' AND S6='1'THEN Q<="0100000";
ELSIF ENA='1' AND S7='1'THEN Q<="1000000";
END IF;
CASE Q IS
WHEN "0000000"=>LED7S<="0000";
WHEN "0000001"=>LED7S<="0001";
WHEN "0000010"=>LED7S<="0010";
WHEN "0000100"=>LED7S<="0011";
WHEN "0001000"=>LED7S<="0100";
WHEN "0010000"=>LED7S<="0101";
WHEN "0100000"=>LED7S<="0110";
WHEN "1000000"=>LED7S<="0111";
WHEN OTHERS=>LED7S<="0000";
END CASE;
END PROCESS A_PRO;
END one;
，编译能通过，但是功能仿真时总是出现Error: Zero-time oscillation in node "|qiangdaqi|LED7S" at time 130.0 ns. Check the design or vector source file for combinational loop.
不知道为什么，希望能够得到帮助，不胜感激~
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