求助 请各位高手解决一下问题
module ZJX ( cout7, cout6, cout5, cout4, cout3, cout2, cout1, cout0,clk, clr,
din7, din6, din5, din4, din3, din2, din1, din0);
input din7, din6, din5, din4, din3, din2, din1, din0;
input clk, clr;
output cout7, cout6, cout5, cout4, cout3, cout2, cout1, cout0;
reg cout7, cout6, cout5, cout4, cout3, cout2, cout1, cout0;
always@ ( posedge clr or posedge clk) begin
if ( clr==1'b1)
begin
cout7<=2'b0; cout6<=2'b0;
cout5<=2'b0; cout4<=2'b0;
cout3<=2'b0; cout2<=2'b0;
cout1<=2'b0; cout0<=2'b0; end
else begin
cout7 <=cout7 ; cout6 <=cout6 ;
cout7 <=din7; cout6 <=din6;
cout5 <=cout5 ; cout4 <=cout4 ;
cout5 <=din5; cout4 <=din4;
cout3 <=cout3 ; cout2 <=cout2 ;
cout3 <=din3; cout2 <=din2;
cout1 <=cout1 ; cout0 <=cout0 ;
cout1 <=din1; cout0 <=din0; end
end
endmodule
这个程序有问题，编译不通过，小的刚开始学verilohdl 语言，看不出来哪错了，谢谢了！
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