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module ZJX ( cout7, cout6, cout5, cout4, cout3, cout2, cout1, cout0,
clk, clr,
din7, din6, din5, din4, din3, din2, din1, din0);
input din7, din6, din5, din4, din3, din2, din1, din0;
input clk, clr;
output[1:0] cout7, cout6, cout5, cout4, cout3, cout2, cout1, cout0;
reg cout7, cout6, cout5, cout4, cout3, cout2, cout1, cout0;
always@ ( posedge clr or posedge clk) begin
if ( clr==1'b1)
begin
cout7<=2'b0; cout6<=2'b0;
cout5<=2'b0; cout4<=2'b0;
cout3<=2'b0; cout2<=2'b0;
cout1<=2'b0; cout0<=2'b0; end
else begin
cout7 [1]<=cout7 [0] ; cout6 [1]<=cout6 [0] ;
cout7 [0]<=din7; cout6 [0]<=din6;
cout5 [1]<=cout5 [0] ; cout4 [1]<=cout4 [0] ;
cout5 [0]<=din5; cout4 [0]<=din4;
cout3 [1]<=cout3 [0] ; cout2 [1]<=cout2 [0] ;
cout3 [0]<=din3; cout2 [0]<=din2;
cout1 [1]<=cout1 [0] ; cout0 [1]<=cout0 [0] ;
cout1 [0]<=din1; cout0 [0]<=din0; end
end
endmodule
这个程序有问题,编译不通过,小的刚开始学verilohdl 语言,看不出来哪错了,谢谢了! |
阿莫论坛20周年了!感谢大家的支持与爱护!!
知道什么是神吗?其实神本来也是人,只不过神做了人做不到的事情 所以才成了神。 (头文字D, 杜汶泽)
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