verilog 代码 访真中出现未知XXXX
请各位帮看一下这段的VERILOG代码为啥,oe,ce,we 会变化时出现一段时间的XXXXXXXX先谢过!
图:
http://cache.amobbs.com/bbs_upload782111/files_35/ourdev_609279TCZGTY.JPG
(原文件名:1图.JPG)
程序段:
module vga(dclk,hs,vs,pspclk3,pspclk1,pspclk,ecudata,ao,wr,oe,ce,we,ramdata,ramaddress,hight);
input dclk,ao,wr;
input ecudata;
output hs,vs,pspclk3,pspclk1,oe,ce,we,pspclk;
output ramaddress;
output hight;
inout ramdata;
reg hs,vs,pspclk1,pspclk3,pspclk;
reg count_v,count_h;
reg flag,j,start,nextstart;
reg cmdreg;
reg weARMADDR,rdARMADDR;
reg ioreg,addl,addh,ramdata;
reg hight1,low1,hight;
reg row,ce,oe,we;
wire si;
reg sysen;
assign endata=(count_h>3&count_h<120)?1:0;
assign ramaddress=row?weARMADDR:rdARMADDR;
assign si=wr;
initial
begin
oe<=1;
ce<=1;
we<=1;
end
//always @(negedge wr)
//begin
// si<=1;
//end
always@ (posedge dclk or negedge si)//or negedge wr
begin
if(!si)
begin
case (start)
0:
begin
if(ao==1)//comm
cmdreg<=ecudata;
else//DATA
begin
if(cmdreg==8'h00)//written low 8bit address command
addl<=ecudata;
else if(cmdreg==8'h02)////written hight 8bit address command
begin
addh<=ecudata;
weARMADDR<={addh,addl};
end
else if(cmdreg==8'h04)//written data;
ioreg<=ecudata;
end
start<=1;
end
1:
begin
ce<=0;oe<=1;we<=0; //input ram
start<=2;row<=1;
end
2:
begin
if(weARMADDR==38399)
weARMADDR<=0;
start<=3;
end
3:
begin
ramdata<=ioreg;
weARMADDR<=weARMADDR+1;
start<=0;ce<=1;
end
endcase
end
else if(endata)
begin
case(nextstart)
0:begin
ce<=0;oe<=0;we<=1;row<=1;
nextstart<=1;
end
1:begin
hight1<=ramdata;low1<=ramdata;
nextstart<=2;
end
2:begin
if(rdARMADDR==38399)
rdARMADDR<=0;
rdARMADDR<=rdARMADDR+1;
nextstart<=3;
end
3:begin
ce<=1;hight<=hight1;
nextstart<=4;
end
4:begin
nextstart<=5;
end
5:begin
nextstart<=6;
end
6:begin
hight<=low1;
nextstart<=7;
end
7:begin
nextstart<=0;
ce<=1;
end
endcase
end
end 自己先顶一下,各位帮看看谢谢 不行了,写的太晦涩难懂了。
请遵守以下2个准则:
1,一个always块中,只对有密切关系的寄存器赋值。最好是只对一个寄存器进行操作。
2,对于一个寄存器,仅在一个always块中赋值。
至于为什么会出不定态,我觉得是因为start没有赋初值的原因。请在这段代码中加入reset的逻辑,不要用initial来赋寄存器的初值。 回复【2楼】ngzhang 兽哥
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我回去试试我想start应该没问题吧呃这是我感觉的 谢啦 我的想法是在DCLK作用下每四个DCLK 完成一次SDRAM写当然在WR有效期 ,当WR无效时,8个DCLK从SDRAM取数输出
大家帮看一下啊闹死我了 将SI的沿检测去掉 就正常了不解。。。。。。。。。
哪位了解VERILOG的兄弟帮看看
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