一个运动控制的游戏系统
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(原文件名:Action1_thumb.jpg) /****************************************************************
* Skyler Schneider ss868 *
* ECE 5760 Final Project *
* Sand Game *
****************************************************************/
// altera message_off 10230
module VGA_Controller (
// Control Signal
input iCLK, // 50.4MHz Clock (PLL from 27MHz clock).
input iRESET, // System reset signal.
// Host Side
input iRed, // Red color of requested pixel.
input iGreen, // Green color of requested pixel.
input iBlue, // Blue color of requested pixel.
output reg oAddress, // Address of pixel request
// (0 to 640*480-1, top-left is 0).
output reg oCoord_X, // X of pixel request (0 to 639, left is 0).
output reg oCoord_Y, // Y of pixel request (0 to 479, top is 0)
output reg oValidReq, // Pixel request is valid (rest of circuit
// Need not reply with iRed, iGreen, iBlue
// if oValidReq is 0).
output reg oSystemState, // Low bit toggles every 50MHz cycle.
// Top bits start at 0 when Coord_X is 0 and
// increment every time oCoord_X increments
// at 25.2MHz. See usage notes in VGA_Param.h.
output reg oNewFrame, // This output is raised for one 50.4MHz cycle
// during the last tick of the last row of
// visible pixels. Can be used for purposes of
// time synchronization to compute next frame
// between drawing frames, or to implement a
// synchronized prev frame/next frame construct
// in two halves of SRAM.
// VGA Side (connect directly to VGA output signals)
output reg oVGA_R,
output reg oVGA_G,
output reg oVGA_B,
output reg oVGA_H_SYNC,
output reg oVGA_V_SYNC,
output oVGA_SYNC,
output oVGA_BLANK
);
`include "VGA_Param.h"
// Most VGA logic runs at 25.2MHz. Prevent updates (stall) during
// first 50.4MHz cycle of each 25.2MHz cycle.
wire stall;
assign stall = ~oSystemState;
// Compute next oSystemState.
always @(posedge iCLK) begin
if(iRESET) begin
oSystemState <= 5'b0;
end
else begin
if(stall) oSystemState <= oSystemState + 5'b1;
else oSystemState <= {lookahead_X, 1'b0}; // variable based on such and such here
end
end
// Internal registers to count VGA virtual position.
// H_Cont (horizontal/X) iterates from 0 to 799.
// V_Cont (vertical/Y) iterates from 0 to 524.
reg H_Cont;
reg V_Cont;
assign oVGA_BLANK = oVGA_H_SYNC & oVGA_V_SYNC;
assign oVGA_SYNC= 1'b0;
// Output Color Generator
always @(posedge iCLK) begin
if(iRESET) begin
oVGA_R <= 0;
oVGA_G <= 0;
oVGA_B <= 0;
end
else if(~stall) begin
// When next H_Cont and V_Cont are within the visible region of the screen,
// assert the color channels appropriately.
if(((H_Cont+1) >= X_START) && ((H_Cont+1) < (X_START + H_SYNC_ACT)) &&
(V_Cont >= Y_START) && (V_Cont < (Y_START + V_SYNC_ACT))) begin
oVGA_R <= iRed;
oVGA_G <= iGreen;
oVGA_B <= iBlue;
end
else begin
oVGA_R <= 0;
oVGA_G <= 0;
oVGA_B <= 0;
end
end
end
// Pixel LUT Address Generator
wire lookahead_X;
wire lookahead_Y;
assign lookahead_X = (H_Cont + X_LATENCY + 2) - X_START;
assign lookahead_Y = V_Cont - Y_START;
always @(posedge iCLK) begin
if(iRESET) begin
oCoord_X<= 0;
oCoord_Y<= 0;
oAddress<= 0;
oValidReq <= 1'b0;
end
else if(~stall) begin
oCoord_X<= lookahead_X;
oCoord_Y<= lookahead_Y;
oAddress<= lookahead_Y * H_SYNC_ACT + lookahead_X;
// If the lookahead pixel is in the visible region of memory,
// the pixel color request is valid.
if(((H_Cont+X_LATENCY+2) >= X_START) && ((H_Cont+X_LATENCY+2) < (X_START + H_SYNC_ACT)) &&
(V_Cont >= Y_START) && (V_Cont < (Y_START + V_SYNC_ACT))) begin
oValidReq <= 1'b1;
end
else begin
oValidReq <= 1'b0;
end
end
end
// H_Sync Generator, Ref. 25.2 MHz Clock
always @(posedge iCLK) begin
if(iRESET) begin
H_Cont <= 0;
oVGA_H_SYNC <= 0;
end
else if(~stall) begin
// H_Sync Counter and Generator
if(H_Cont < H_SYNC_MAX) begin
if(H_Cont == (H_SYNC_CYC-1)) begin
oVGA_H_SYNC <= 1;
end
H_Cont <= H_Cont + 10'b1;
end
else begin
H_Cont <= 0;
oVGA_H_SYNC <= 0;
end
end
end
// V_Sync Generator, Ref. H_Sync
always @(posedge iCLK) begin
if(iRESET) begin
V_Cont <= 0;
oVGA_V_SYNC <= 0;
end
else if(~stall) begin
// When H_Sync restarts
if(H_Cont == H_SYNC_MAX) begin
// V_Sync Counter and Generator
if(V_Cont < V_SYNC_MAX) begin
if(V_Cont == (V_SYNC_CYC-1)) begin
oVGA_V_SYNC <= 1;
end
V_Cont <= V_Cont + 10'b1;
end
else begin
V_Cont <= 0;
oVGA_V_SYNC <= 0;
end
end
end
end
// Raise oNewFrame once per frame, after drawing last visible row.
always @(posedge iCLK) begin
oNewFrame <= (H_Cont == H_SYNC_MAX) && (V_Cont - Y_START == V_SYNC_ACT-1) && (~stall);
end
endmodule
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(原文件名:P1000948_med.jpg) /****************************************************************
* Skyler Schneider ss868 *
* ECE 5760 Final Project *
* Sand Game *
****************************************************************/
// Horizontal Parameter ( Pixel )
parameter H_SYNC_CYC = 95;
parameter H_SYNC_BACK= 60;
parameter H_SYNC_ACT = 640; // 640 pixels of content
parameter H_SYNC_FRONT = 5;
parameter H_SYNC_MAX = 799; // 800 effective pixels (cycles)
// Virtical Parameter ( Line )
parameter V_SYNC_CYC = 2;
parameter V_SYNC_BACK= 31;
parameter V_SYNC_ACT = 480; // 480 lines of content
parameter V_SYNC_FRONT = 12;
parameter V_SYNC_MAX = 524; // 525 effective lines
// Start Offset
parameter X_START = H_SYNC_CYC + H_SYNC_BACK;
parameter Y_START = V_SYNC_CYC + V_SYNC_BACK;
// Latency
// If you want to set iRed one 25.2MHz cycle after oAddress, oCoord_X, and
// Coord_Y are set, then choose 1. If you want to set iRed two cycles after
// oAddress etc. are set, then choose 2. If you instead want to set iRed as
// combinationally dependent on oAddress, then choose 0.
parameter X_LATENCY = 3;
// About oSystemState:
//
// If you store a pixel as 16 bits in SRAM, then whenever oSystemState is
// 0, you need to read a new 16-bit word from SRAM. Otherwise the rest of the
// circuit can drive SRAM.
//
// If you store a pixel as 8 bits in SRAM, then whenever oSystemState is
// 0, you need to read a new 16-bit word from SRAM, which will last you for the
// next pixel as well. Otherwise the rest of the circuit can drive SRAM.
//
// If you store a pixel as 4 bits in SRAM, then whenever oSystemState is
// 0, you need to read a new 16-bit word from SRAM, which will last you for the
// next three pixels as well. Otherwise the rest of the circuit can drive SRAM.
//
// If you store a pixel as 2 bits in SRAM, then whenever oSystemState is
// 0, you need to read a new 16-bit word from SRAM, which will last you for the
// next seven pixels as well. Otherwise the rest of the circuit can drive SRAM.
//
// If you store a pixel as 1 bit in SRAM, then whenever oSystemState is
// 0, you need to read a new 16-bit word from SRAM, which will last you for the
// next fifteen pixels as well. Otherwise the rest of the circuit can drive SRAM.
//
// NOTE THAT FOR ALL CASES WITH SRAM SHARING, you will need to buffer the value
// loaded from SRAM each time the low order bits of oSystemState are 0, so
// there will be at least one 25.2MHz cycle delay between oAddress and
// iRed, iGreen, and iBlue. This makes it impractical to set X_LATENCY to 0.
//
// Also keep in mind that X_LATENCY counts in 25.2MHz ticks, whereas oSystemState
// updates at 50.4MHz. Make sure that the values of iRed, iGreen, and iBlue align
// in time such that they are held for two 50.4MHz cycles.
//
// Timing example where X_LATENCY = 2 (don't view with wordwrap):
// 50.4MHz tick #: | -2 | -1 |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 |
// oSystemState: | 30 | 31 |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 |0 |1 |2 |3 |4 |5 |
// oAddress: |? |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 |
// oValidReq: |0 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |
// iRed, iGreen,
// iBlue contain
// color info
// for pixel #: |? |? |? |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 |
// Designer is responsible for making iRed, iGreen, iBlue match timing in last row. // megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: VGA_PLL.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 218 06/27/2010 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors.Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module VGA_PLL (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire sub_wire0;
wire sub_wire5 = 1'h0;
wire sub_wire2 = sub_wire0;
wire sub_wire1 = sub_wire0;
wirec0 = sub_wire1;
wirec1 = sub_wire2;
wiresub_wire3 = inclk0;
wire sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 15,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 14,
altpll_component.clk0_phase_shift = "-9921",
altpll_component.clk1_divide_by = 15,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 28,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "15"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "15"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.200001"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.400002"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "14"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "28"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.20000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-90.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "VGA_PLL.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "15"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "14"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-9921"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "15"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "28"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_PLL.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_PLL.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_PLL.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_PLL.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_PLL_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_PLL_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_PLL_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_PLL_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_PLL.ppf TRUE
// Retrieval info: LIB_FILE: altera_mf /****************************************************************
* Skyler Schneider ss868 *
* ECE 5760 Final Project *
* Sand Game *
****************************************************************/
module DE2_TOP (
// Clock Input
input CLOCK_27, // 27 MHz
input CLOCK_50, // 50 MHz
input EXT_CLOCK, // External Clock
// Push Button
inputKEY, // Pushbutton
// DPDT Switch
input SW, // Toggle Switch
// 7-SEG Display
output HEX0, // Seven Segment Digit 0
output HEX1, // Seven Segment Digit 1
output HEX2, // Seven Segment Digit 2
output HEX3, // Seven Segment Digit 3
output HEX4, // Seven Segment Digit 4
output HEX5, // Seven Segment Digit 5
output HEX6, // Seven Segment Digit 6
output HEX7, // Seven Segment Digit 7
// LED
output LEDG, // LED Green
output LEDR, // LED Red
// UART
output UART_TXD, // UART Transmitter
input UART_RXD, // UART Receiver
// IRDA
output IRDA_TXD, // IRDA Transmitter
input IRDA_RXD, // IRDA Receiver
// SDRAM Interface
inout DRAM_DQ, // SDRAM Data bus 16 Bits
output DRAM_ADDR, // SDRAM Address bus 12 Bits
output DRAM_LDQM, // SDRAM Low-byte Data Mask
output DRAM_UDQM, // SDRAM High-byte Data Mask
output DRAM_WE_N, // SDRAM Write Enable
output DRAM_CAS_N,// SDRAM Column Address Strobe
output DRAM_RAS_N,// SDRAM Row Address Strobe
output DRAM_CS_N, // SDRAM Chip Select
output DRAM_BA_0, // SDRAM Bank Address 0
output DRAM_BA_1, // SDRAM Bank Address 0
output DRAM_CLK, // SDRAM Clock
output DRAM_CKE, // SDRAM Clock Enable
// Flash Interface
inoutFL_DQ, // FLASH Data bus 8 Bits
output FL_ADDR, // FLASH Address bus 22 Bits
output FL_WE_N, // FLASH Write Enable
output FL_RST_N, // FLASH Reset
output FL_OE_N, // FLASH Output Enable
output FL_CE_N, // FLASH Chip Enable
// SRAM Interface
inout SRAM_DQ, // SRAM Data bus 16 Bits
output SRAM_ADDR, // SRAM Address bus 18 Bits
output SRAM_UB_N, // SRAM High-byte Data Mask
output SRAM_LB_N, // SRAM Low-byte Data Mask
output SRAM_WE_N, // SRAM Write Enable
output SRAM_CE_N, // SRAM Chip Enable
output SRAM_OE_N, // SRAM Output Enable
// ISP1362 Interface
inout OTG_DATA, // ISP1362 Data bus 16 Bits
output OTG_ADDR, // ISP1362 Address 2 Bits
output OTG_CS_N, // ISP1362 Chip Select
output OTG_RD_N, // ISP1362 Write
output OTG_WR_N, // ISP1362 Read
output OTG_RST_N, // ISP1362 Reset
output OTG_FSPEED,// USB Full Speed, 0 = Enable, Z = Disable
output OTG_LSPEED,// USB Low Speed,0 = Enable, Z = Disable
input OTG_INT0, // ISP1362 Interrupt 0
input OTG_INT1, // ISP1362 Interrupt 1
input OTG_DREQ0, // ISP1362 DMA Request 0
input OTG_DREQ1, // ISP1362 DMA Request 1
output OTG_DACK0_N, // ISP1362 DMA Acknowledge 0
output OTG_DACK1_N, // ISP1362 DMA Acknowledge 1
// LCD Module 16X2
inoutLCD_DATA, // LCD Data bus 8 bits
output LCD_ON, // LCD Power ON/OFF
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
// SD Card Interface
inout SD_DAT, // SD Card Data
inout SD_DAT3, // SD Card Data 3
inout SD_CMD, // SD Card Command Signal
output SD_CLK, // SD Card Clock
// I2C
inout I2C_SDAT, // I2C Data
output I2C_SCLK, // I2C Clock
// PS2
input PS2_DAT, // PS2 Data
input PS2_CLK, // PS2 Clock
// USB JTAG link
input TDI, // CPLD -> FPGA (data in)
input TCK, // CPLD -> FPGA (clk)
input TCS, // CPLD -> FPGA (CS)
output TDO, // FPGA -> CPLD (data out)
// VGA
output VGA_CLK, // VGA Clock
output VGA_HS, // VGA H_SYNC
output VGA_VS, // VGA V_SYNC
output VGA_BLANK, // VGA BLANK
output VGA_SYNC, // VGA SYNC
output VGA_R, // VGA Red
output VGA_G, // VGA Green
output VGA_B, // VGA Blue
// Ethernet Interface
inout ENET_DATA, // DM9000A DATA bus 16Bits
output ENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
output ENET_CS_N, // DM9000A Chip Select
output ENET_WR_N, // DM9000A Write
output ENET_RD_N, // DM9000A Read
output ENET_RST_N,// DM9000A Reset
input ENET_INT, // DM9000A Interrupt
output ENET_CLK, // DM9000A Clock 25 MHz
// Audio CODEC
inout AUD_ADCLRCK, // Audio CODEC ADC LR Clock
input AUD_ADCDAT,// Audio CODEC ADC Data
inout AUD_DACLRCK, // Audio CODEC DAC LR Clock
output AUD_DACDAT,// Audio CODEC DAC Data
inout AUD_BCLK, // Audio CODEC Bit-Stream Clock
output AUD_XCK, // Audio CODEC Chip Clock
// TV Decoder
inputTD_DATA, // TV Decoder Data bus 8 bits
input TD_HS, // TV Decoder H_SYNC
input TD_VS, // TV Decoder V_SYNC
output TD_RESET, // TV Decoder Reset
// GPIO
inout GPIO_0, // GPIO Connection 0
inout GPIO_1 // GPIO Connection 1
);
//Turn off all displays.
assign HEX0 = 7'h7F;
assign HEX1 = 7'h7F;
assign HEX2 = 7'h7F;
assign HEX3 = 7'h7F;
assign HEX4 = 7'h7F;
assign HEX5 = 7'h7F;
assign HEX6 = 7'h7F;
assign HEX7 = 7'h7F;
assign LEDR = 18'h0;
assign LEDG = 9'h0;
//Set all GPIO to tri-state.
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;
//Disable audio codec.
assign AUD_DACDAT = 1'b0;
assign AUD_XCK = 1'b0;
//Disable DRAM.
assign DRAM_ADDR= 12'h0;
assign DRAM_BA_0= 1'b0;
assign DRAM_BA_1= 1'b0;
assign DRAM_CAS_N = 1'b1;
assign DRAM_CKE = 1'b0;
assign DRAM_CLK = 1'b0;
assign DRAM_CS_N= 1'b1;
assign DRAM_DQ = 16'hzzzz;
assign DRAM_LDQM= 1'b0;
assign DRAM_RAS_N = 1'b1;
assign DRAM_UDQM= 1'b0;
assign DRAM_WE_N= 1'b1;
//Disable Ethernet.
assign ENET_CLK = 1'b0;
assign ENET_CS_N= 1'b1;
assign ENET_CMD = 1'b0;
assign ENET_DATA= 16'hzzzz;
assign ENET_RD_N= 1'b1;
assign ENET_RST_N = 1'b1;
assign ENET_WR_N= 1'b1;
//Disable flash.
assign FL_ADDR= 22'h0;
assign FL_CE_N= 1'b1;
assign FL_DQ = 8'hzz;
assign FL_OE_N= 1'b1;
assign FL_RST_N = 1'b1;
assign FL_WE_N= 1'b1;
//Disable LCD.
assign LCD_BLON = 1'b0;
assign LCD_DATA = 8'hzz;
assign LCD_EN = 1'b0;
assign LCD_ON = 1'b0;
assign LCD_RS = 1'b0;
assign LCD_RW = 1'b0;
//Disable OTG.
assign OTG_ADDR = 2'h0;
assign OTG_CS_N = 1'b1;
assign OTG_DACK0_N = 1'b1;
assign OTG_DACK1_N = 1'b1;
assign OTG_FSPEED= 1'b1;
assign OTG_DATA = 16'hzzzz;
assign OTG_LSPEED= 1'b1;
assign OTG_RD_N = 1'b1;
assign OTG_RST_N = 1'b1;
assign OTG_WR_N = 1'b1;
//Disable SDRAM.
assign SD_DAT = 1'bz;
assign SD_CLK = 1'b0;
//Disable all other peripherals.
assign I2C_SCLK = 1'b0;
assign IRDA_TXD = 1'b0;
//assign TD_RESET = 1'b0;
assign TDO = 1'b0;
assign UART_TXD = 1'b0;
/**************************************************
* Clock and Reset Generation *
**************************************************/
wire SYSTEM_CLK;
VGA_PLL p1 (
.inclk0 (CLOCK_27),
.c0 (VGA_CLK),
.c1 (SYSTEM_CLK)
);
wire DLY_RST;
Reset_Delay r0 (
.iCLK (SYSTEM_CLK),
.oRESET (DLY_RST)
);
wire Reset;
assign Reset = ~DLY_RST;
/**************************************************
* Random Number Generator *
**************************************************/
wire wRand4;
RNG_4b rng0 (
.iCLK (SYSTEM_CLK),
.iReset (Reset),
.oRandomNum (wRand4)
);
/**************************************************
* VGA Control Logic *
**************************************************/
assign TD_RESET = 1'b1; // Allow 27 MHz
wire wVGA_R;
wire wVGA_G;
wire wVGA_B;
wire wVGA_ADDR;
wire wVGA_X;
wire wVGA_Y;
wire wNewFrame;
wire wSystemState;
VGA_Controller u1 (
// Control Signal
.iCLK (SYSTEM_CLK),
.iRESET (Reset),
// Host Side
.iRed (wVGA_R),
.iGreen (wVGA_G),
.iBlue (wVGA_B),
.oAddress (wVGA_ADDR),
.oCoord_X (wVGA_X),
.oCoord_Y (wVGA_Y),
.oSystemState (wSystemState),
.oNewFrame (wNewFrame),
// VGA Side
.oVGA_R (VGA_R),
.oVGA_G (VGA_G),
.oVGA_B (VGA_B),
.oVGA_H_SYNC (VGA_HS),
.oVGA_V_SYNC (VGA_VS),
.oVGA_SYNC (VGA_SYNC),
.oVGA_BLANK (VGA_BLANK)
);
wire wSRAM_Color;
ColorSelector cs0 (
.iCLK (SYSTEM_CLK),
.iSystemState(wSystemState),
.iVGA_X (wVGA_X),
.iVGA_Y (wVGA_Y),
.iSRAM_Color (wSRAM_Color),
.iCursor_X (wCursorX),
.iCursor_Y (wCursorY),
.iCursor_Size(wCursorSize),
.iTrollColor (wTrollColor),
.oVGA_R (wVGA_R),
.oVGA_G (wVGA_G),
.oVGA_B (wVGA_B)
);
/**************************************************
* SRAM Arbitration *
**************************************************/
SRAM_Controller sc0 (
.iCLK (SYSTEM_CLK),
.iRESET (Reset),
.iSystemState(wSystemState),
.iNewFrame (wNewFrame),
.iVGA_ADDR (wVGA_ADDR),
.oVGA_Color (wSRAM_Color),
.iCA_ReadAddr(wCA_ReadAddr),
.oCA_ReadData(wCA_ReadData),
.iCA_WriteAddr (wCA_WriteAddr),
.iCA_WriteData (wCA_WriteData),
.iCA_WriteEn (wCA_WriteEn),
.SRAM_DQ (SRAM_DQ),
.oSRAM_ADDR (SRAM_ADDR),
.oSRAM_UB_N (SRAM_UB_N),
.oSRAM_LB_N (SRAM_LB_N),
.oSRAM_WE_N (SRAM_WE_N),
.oSRAM_CE_N (SRAM_CE_N),
.oSRAM_OE_N (SRAM_OE_N)
);
/**************************************************
* CA State Machine *
**************************************************/
wire wCA_ReadAddr;
wire wCA_ReadData;
wire wCA_WriteAddr;
wire wCA_WriteData;
wire wCA_WriteEn;
CA_Controller cc0 (
.iCLK (SYSTEM_CLK),
.iRESET (wFrameReset),
.iSTALL (wFrameHold),
.iSystemState (wSystemState),
.iNewFrame (wNewFrame),
.iRand4 (wRand4),
.iTrollFlame (wTrollFlame),
.iCursorColor (wCursorColor),
.iCursorSize (wCursorSize),
.iCursorX (wCursorX),
.iCursorY (wCursorY),
.iCursorDraw (wCursorDraw),
.iFaucetSize_SAND(wFaucetSize_SAND),
.iFaucetSize_WATER (wFaucetSize_WATER),
.iFaucetSize_SALT(wFaucetSize_SALT),
.iFaucetSize_OIL (wFaucetSize_OIL),
.oReadAddr (wCA_ReadAddr),
.iReadData (wCA_ReadData),
.oWriteAddr (wCA_WriteAddr),
.oWriteData (wCA_WriteData),
.oWriteEn (wCA_WriteEn)
);
/**************************************************
* User Input *
**************************************************/
wire wKeyboardEventReady;
wire wKeyboardEventType;
Keyboard_Controller kc0 (
.iPS2_CLK (PS2_CLK),
.iPS2_DAT (PS2_DAT),
.iCLK (SYSTEM_CLK),
.iRESET (Reset),
.oEventReady (wKeyboardEventReady),
.oEventType(wKeyboardEventType)
);
wire wCursorColor;
wire wCursorSize;
wire wCursorX;
wire wCursorY;
wire wCursorDraw;
wire wFrameReset;
wire wFrameHold;
wire wTrollBegin;
wire wFaucetSize_SAND;
wire wFaucetSize_WATER;
wire wFaucetSize_SALT;
wire wFaucetSize_OIL;
Input_Controller ic0 (
.iCLK (SYSTEM_CLK),
.iRESET (Reset),
.iSystemState (wSystemState),
.iNewFrame (wNewFrame),
.iSW (SW),
.iKEY (KEY),
.iEventReady (wKeyboardEventReady),
.iEventType (wKeyboardEventType),
.oCursorColor (wCursorColor),
.oCursorSize (wCursorSize),
.oCursorX (wCursorX),
.oCursorY (wCursorY),
.oCursorDraw (wCursorDraw),
.oFaucetSize_SAND(wFaucetSize_SAND),
.oFaucetSize_WATER (wFaucetSize_WATER),
.oFaucetSize_SALT(wFaucetSize_SALT),
.oFaucetSize_OIL (wFaucetSize_OIL),
.oFrameReset (wFrameReset),
.oFrameHold (wFrameHold),
.oTrollBegin (wTrollBegin)
);
wire wTrollFlame;
wire wTrollColor;
Troll_Controller tc0 (
.iCLK (SYSTEM_CLK),
.iRESET (wFrameReset),
.iSTALL (wFrameHold),
.iNewFrame (wNewFrame),
.iTrollBegin (wTrollBegin),
.iVGA_X (wVGA_X),
.iVGA_Y (wVGA_Y),
.oTrollFlame (wTrollFlame),
.oTrollColor (wTrollColor)
);
endmodule 实验室环境不错。。还有美女 http://cache.amobbs.com/bbs_upload782111/files_35/ourdev_609148HUCREV.png
(原文件名:block.png)
http://cache.amobbs.com/bbs_upload782111/files_35/ourdev_609149Q2TFJK.png
(原文件名:sandcap.png) 工作环境不错
羡慕
~~~~
代码没看
看图片
ms
开发了一个图像识别,轨迹运算
的东西
简言之
好像是对着墙打乒乓球
是吧~~~~ 膜拜! 膜拜! 神? 很好的开发环境~公司很有钱啊,羡慕ing Tomas Yung 你的《FPGA实现音频可视化》我什么都看不见
你没看见是0回复吗?
重新发一个吧 mark 神奇啊 回复【11楼】adsladsl
很好的开发环境~公司很有钱啊,羡慕ing
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不是公司,是康奈尔大学的实验室,ECE-5670课程的课题设计。一般1-3个人做一个项目。 在苏州?嘛地方,有时间去拜访下~~ Tomas Yung 能提供个原理图看看吗 关注。。。 关注~ 膜拜! 牛
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