Verilog大虾帮我看下这段代码，下载后怎么会出现这样的问题？
我这段代码下载到板子上，LED怎么只轮流显示1,3,5,7,9啊？module count_led
( input o,
output p_bus,
output st
);
reg j=0;
reg p=0;
reg ld;
assign p_bus = ld;
assign st = 6'b111101;
always @(posedge o)
begin
if(j<9)j <= j+1;
else
begin
if(p<10)
begin
p <= p+1;
j <= 0;
end
else p <= 0;
end
end
always@(posedge p)
begin
case ( p )
8'h0 : ld =8'HC0 ;
8'h1 : ld =8'HF9 ;
8'h2 : ld =8'HA4 ;
8'h3 : ld =8'HB0 ;
8'h4 : ld =8'H99 ;
8'h5 : ld =8'H92 ;
8'h6 : ld =8'H82 ;
8'h7 : ld =8'HF8 ;
8'h8 : ld =8'H80 ;
8'h9 : ld =8'H90 ;
defaultld =8'H96 ;
endcase
end
endmodule 我这段代码下载到板子上，LED怎么只轮流显示1,3,5,7,9啊？
module count_led
( input o,
output p_bus,
output st
);
reg j=0;
reg p=0;
reg ld;
assign p_bus = ld;
assign st = 6'b111101;
always @(posedge o)
begin
if(j<9)
j <= j+1;
else
begin
if(p<10)
begin
p <= p+1;
j <= 0;
end
else
p <= 0;
end
end
always@(posedge p)
begin
case ( p )
8'h0 : ld =8'HC0 ;
8'h1 : ld =8'HF9 ;
8'h2 : ld =8'HA4 ;
8'h3 : ld =8'HB0 ;
8'h4 : ld =8'H99 ;
8'h5 : ld =8'H92 ;
8'h6 : ld =8'H82 ;
8'h7 : ld =8'HF8 ;
8'h8 : ld =8'H80 ;
8'h9 : ld =8'H90 ;
defaultld =8'H96 ;
endcase
end
endmodule
改这句：always@(posedge p)
改为：always@( p )
试一下，行不行 这样一改也可的
reg型的数据好像不能用来作为上升沿触发信号
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