有CPLD经验的师傅们指点一下
本人最近在做一个利用CPLD控制的软启动器，但是出现了一些问题，奇怪的是我把程序下载到我的FPGA开发板上后，输出的波形是正确的，我把程序下载到CPLD上面的时候，晶振波形输入正确，Xlinx显示下载成功，但是CPLD引脚没什么输出，而且我对输入输出引脚进行设置了，找了好长时间也没找到原因，显示下载成功但没有输出，这是我程序下载到CPLD上时截的一些图，大家帮我看看
http://cache.amobbs.com/bbs_upload782111/files_33/ourdev_582416BP2ZJ9.jpg
(原文件名:O2(H26AQ)$VEA@SXKZE3B2W.jpg)
http://cache.amobbs.com/bbs_upload782111/files_33/ourdev_582418ZGA4ZT.jpg
(原文件名:}ZY51LML2I](PV1NS}X0(YR.jpg)
http://cache.amobbs.com/bbs_upload782111/files_33/ourdev_582419FGI1AJ.jpg
(原文件名:%F{NL6QWWP%ANPXZUM``~P5.jpg)
http://cache.amobbs.com/bbs_upload782111/files_33/ourdev_582420W62SCK.jpg
(原文件名:H}LPJJK)DQPL0TZ4%[(AJ@R.jpg)
这是我在Xilinx中对引脚的设置，
http://cache.amobbs.com/bbs_upload782111/files_33/ourdev_582422LX183S.jpg
(原文件名:MQ{9_P]{}8_0$D)QKN 怀疑你下的文件不对，下了另一个文件 那个程序可以下载到FPGA中去，而且输出波形也正确，程序上应该没什么问题，
http://cache.amobbs.com/bbs_upload782111/files_33/ourdev_582429FJ3UZ5.jpg
(原文件名:DHMEY8XBBZZN078QT.jpg)
http://cache.amobbs.com/bbs_upload782111/files_33/ourdev_582431BMTPM5.jpg
(原文件名:9U52 回复【1楼】888888888888
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这个我可以确定，文件没有下载错误 回复【楼主位】haixiaowujun
------------------------------------------------------------------------------------------------------ 回复【1楼】888888888888
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就是下载那个文件 综合后，FPGA文件应当与CPLD的不一样的，你不会是把给FPGA用的下到CPLD中吧 给看看综合报告呗。 回复【7楼】ngzhang 兽哥哦
-----------------------------------------------------------------------
这是CPLD的综合
Release 9.2i - xst J.36
Copyright (c) 1995-2007 Xilinx, Inc.All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.39 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.39 s | Elapsed : 0.00 / 0.00 s
--> Reading design: haller.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "haller.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "haller"
Output Format : NGC
Target Device : XC9500 CPLDs
---- Source Options
Top Module Name : haller
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
Mux Extraction : YES
Resource Sharing : YES
---- Target Options
Add IO Buffers : YES
MACRO Preserve : YES
XOR Preserve : YES
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : haller.lso
Keep Hierarchy : YES
RTL Output : Yes
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Verilog 2001 : YES
---- Other Options
wysiwyg : NO
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "haller.v" in library work
Module <haller> compiled
No errors in compilation
Analysis of file <"haller.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <haller> in library <work>.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <haller>.
Module <haller> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
INFO:Xst:2679 - Register <b2> in unit <haller> has a constant value of 0000011000111111 during circuit operation. The register is replaced by logic.
Synthesizing Unit <haller>.
Related source file is "haller.v".
Found 6-bit register for signal <pwm>.
Found 16-bit up counter for signal <cnt1>.
Found 16-bit comparator less for signal <pwm$cmp_lt0000> created at line 44.
Summary:
inferred 1 Counter(s).
inferred 1 Comparator(s).
Unit <haller> synthesized.
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Counters : 1
16-bit up counter : 1
# Registers : 1
6-bit register : 1
# Comparators : 1
16-bit comparator less : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
WARNING:Xst:1710 - FF/Latch<0> (without init value) has a constant value of 0 in block <2>.
WARNING:Xst:1710 - FF/Latch<0> (without init value) has a constant value of 0 in block <3>.
WARNING:Xst:1710 - FF/Latch<0> (without init value) has a constant value of 0 in block <4>.
WARNING:Xst:1710 - FF/Latch<0> (without init value) has a constant value of 0 in block <5>.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Counters : 1
16-bit up counter : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1710 - FF/Latch<pwm_2> (without init value) has a constant value of 0 in block <haller>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch<pwm_3> (without init value) has a constant value of 0 in block <haller>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch<pwm_4> (without init value) has a constant value of 0 in block <haller>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch<pwm_5> (without init value) has a constant value of 0 in block <haller>.
Optimizing unit <haller> ...
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : haller.ngr
Top Level Output File Name : haller
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : YES
Target Technology : XC9500 CPLDs
Macro Preserve : YES
XOR Preserve : YES
wysiwyg : NO
Design Statistics
# IOs : 8
Cell Usage :
# BELS : 102
# AND2 : 36
# AND3 : 2
# AND8 : 2
# GND : 1
# INV : 42
# OR2 : 2
# OR3 : 1
# OR6 : 1
# XOR2 : 15
# FlipFlops/Latches : 18
# FD : 18
# IO Buffers : 8
# IBUF : 2
# OBUF : 6
=========================================================================
CPU : 2.67 / 3.09 s | Elapsed : 3.00 / 3.00 s
-->
Total memory usage is 118764 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 9 ( 0 filtered)
Number of infos : 1 ( 0 filtered) 回复【6楼】888888888888
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这个应该不会的 回复【7楼】ngzhang 兽哥
-----------------------------------------------------------------------
这是在FPGA中的综合报告
Release 9.2i - xst J.36
Copyright (c) 1995-2007 Xilinx, Inc.All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.27 s | Elapsed : 0.00 / 1.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.27 s | Elapsed : 0.00 / 1.00 s
--> Reading design: sss.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "sss.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "sss"
Output Format : NGC
Target Device : xc3s400-5-pq208
---- Source Options
Top Module Name : sss
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : sss.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "sss.v" in library work
Module <sss> compiled
No errors in compilation
Analysis of file <"sss.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <sss> in library <work>.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <sss>.
Module <sss> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
INFO:Xst:2679 - Register <b2> in unit <sss> has a constant value of 0000011000111111 during circuit operation. The register is replaced by logic.
Synthesizing Unit <sss>.
Related source file is "sss.v".
Found 6-bit register for signal <pwm>.
Found 16-bit up counter for signal <cnt1>.
Found 16-bit comparator less for signal <pwm$cmp_lt0000> created at line 44.
Summary:
inferred 1 Counter(s).
inferred 6 D-type flip-flop(s).
inferred 1 Comparator(s).
Unit <sss> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Counters : 1
16-bit up counter : 1
# Registers : 1
6-bit register : 1
# Comparators : 1
16-bit comparator less : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Loading device for application Rf_Device from file '3s400.nph' in environment E:\Xilinx.
WARNING:Xst:1710 - FF/Latch<pwm_2> (without init value) has a constant value of 0 in block <sss>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch<pwm_3> (without init value) has a constant value of 0 in block <sss>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch<pwm_4> (without init value) has a constant value of 0 in block <sss>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch<pwm_5> (without init value) has a constant value of 0 in block <sss>.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Counters : 1
16-bit up counter : 1
# Registers : 2
Flip-Flops : 2
# Comparators : 1
16-bit comparator less : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <sss> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block sss, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 18
Flip-Flops : 18
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : sss.ngr
Top Level Output File Name : sss
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 8
Cell Usage :
# BELS : 73
# GND : 1
# INV : 4
# LUT1 : 16
# LUT2 : 3
# LUT3 : 1
# LUT4 : 6
# MUXCY : 26
# VCC : 1
# XORCY : 15
# FlipFlops/Latches : 18
# FDR : 17
# FDRS : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 7
# IBUF : 1
# OBUF : 6
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s400pq208-5
Number of Slices: 16out of 3584 0%
Number of Slice Flip Flops: 18out of 7168 0%
Number of 4 input LUTs: 30out of 7168 0%
Number of IOs: 8
Number of bonded IOBs: 8out of 141 5%
Number of GCLKs: 1out of 8 12%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name)| Load|
-----------------------------------+------------------------+-------+
clk | BUFGP | 18 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 6.314ns (Maximum Frequency: 158.373MHz)
Minimum input arrival time before clock: 6.181ns
Maximum output required time after clock: 6.216ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 6.314ns (frequency: 158.373MHz)
Total number of paths / destination ports: 424 / 34
-------------------------------------------------------------------------
Delay: 6.314ns (Levels of Logic = 7)
Source: cnt1_4 (FF)
Destination: cnt1_1 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: cnt1_4 to cnt1_1
Gate Net
Cell:in->out fanout Delay DelayLogical Name (Net Name)
----------------------------------------------------
FDR:C->Q 3 0.626 1.066cnt1_4 (cnt1_4)
LUT1:I0->O 1 0.479 0.000cnt1_and0000_wg_cy<0>_rt (cnt1_and0000_wg_cy<0>_rt)
MUXCY:S->O 1 0.435 0.000cnt1_and0000_wg_cy<0> (cnt1_and0000_wg_cy<0>)
MUXCY:CI->O 1 0.056 0.000cnt1_and0000_wg_cy<1> (cnt1_and0000_wg_cy<1>)
MUXCY:CI->O 1 0.056 0.000cnt1_and0000_wg_cy<2> (cnt1_and0000_wg_cy<2>)
MUXCY:CI->O 1 0.056 0.000cnt1_and0000_wg_cy<3> (cnt1_and0000_wg_cy<3>)
MUXCY:CI->O 2 0.246 0.915cnt1_and0000_wg_cy<4> (cnt1_and0000)
LUT2:I1->O 15 0.479 1.010Mcount_cnt1_val1 (Mcount_cnt1_val)
FDR:R 0.892 cnt1_1
----------------------------------------
Total 6.314ns (3.323ns logic, 2.991ns route)
(52.6% logic, 47.4% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 34 / 19
-------------------------------------------------------------------------
Offset: 6.181ns (Levels of Logic = 4)
Source: rst (PAD)
Destination: cnt1_1 (FF)
Destination Clock: clk rising
Data Path: rst to cnt1_1
Gate Net
Cell:in->out fanout Delay DelayLogical Name (Net Name)
----------------------------------------------------
IBUF:I->O 3 0.715 1.066rst_IBUF (rst_IBUF)
LUT4:I0->O 1 0.479 0.000cnt1_and0000_wg_lut<4> (N3)
MUXCY:S->O 2 0.625 0.915cnt1_and0000_wg_cy<4> (cnt1_and0000)
LUT2:I1->O 15 0.479 1.010Mcount_cnt1_val1 (Mcount_cnt1_val)
FDR:R 0.892 cnt1_1
----------------------------------------
Total 6.181ns (3.190ns logic, 2.991ns route)
(51.6% logic, 48.4% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 6.216ns (Levels of Logic = 1)
Source: pwm_1 (FF)
Destination: pwm<1> (PAD)
Source Clock: clk rising
Data Path: pwm_1 to pwm<1>
Gate Net
Cell:in->out fanout Delay DelayLogical Name (Net Name)
----------------------------------------------------
FDR:C->Q 1 0.626 0.681pwm_1 (pwm_1)
OBUF:I->O 4.909 pwm_1_OBUF (pwm<1>)
----------------------------------------
Total 6.216ns (5.535ns logic, 0.681ns route)
(89.0% logic, 11.0% route)
=========================================================================
CPU : 4.72 / 5.09 s | Elapsed : 4.00 / 5.00 s
-->
Total memory usage is 139752 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 4 ( 0 filtered)
Number of infos : 1 ( 0 filtered) 看错了，删除 我的loc前面没有s:的:
NET "nRST" LOC = "p143" ; 回复【12楼】qinxg
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我的FPGA上的LOC也和你一样，没有S的 回复【12楼】qinxg
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我那个带S的是自动生成的，
我开始是这样写的：
NET "clk"LOC ="P5";
NET "rst"LOC="P39";
NET "pwm" LOC="P35";
综合后就出现下面的.ucf：
#NET "clk"LOC ="P5";
#NET "rst"LOC="P39";
#NET "pwm" LOC="P35";
#PINLOCK_BEGIN
#Mon Sep 13 09:52:18 2010
NET "clk" LOC ="S:PIN5";
NET "rst" LOC ="S:PIN39";
NET "pwm" LOC ="S:PIN35";
#PINLOCK_END
不知你之前遇到过没有啊 这样比较难判断，建议lz先写一个小的code，下载到cpld中，判断片子没有问题 回复【5楼】haixiaowujun
----------------------------------------------------------------------- 回复【5楼】haixiaowujun
----------------------------------------------------------------------- 回复【1楼】888888888888
-----------------------------------------------------------------------
问你个问题，今天我用ISE10.1的版本，
结果发现一个问题，也是可以下载，没有输出结果（用的一个简单的程序）
但发现一个问题，
http://cache.amobbs.com/bbs_upload782111/files_33/ourdev_583022LP264J.jpg
(原文件名:P}6W9ESFWNEH{NUE7
我原先的是ISE9.2版的，那个Lock Pins是可以通过的，不知怎么这次就通不过了，那个错误研究了很长时间，但还是不知怎么改 回复【7楼】ngzhang 兽哥
-----------------------------------------------------------------------
问你个问题，今天我用ISE10.1的版本，
结果发现一个问题，也是可以下载，没有输出结果（用的一个简单的程序）
但发现一个问题，
http://cache.amobbs.com/bbs_upload782111/files_33/ourdev_583022LP264J.jpg
(原文件名:P}6W9ESFWNEH{NUE7
我原先的是ISE9.2版的，那个Lock Pins是可以通过的，不知怎么这次就通不过了，那个错误研究了很长时间，但还是不知怎么改 回复【12楼】qinxg
-----------------------------------------------------------------------
问你个问题，今天我用ISE10.1的版本，
结果发现一个问题，也是可以下载，没有输出结果（用的一个简单的程序）
但发现一个问题，
http://cache.amobbs.com/bbs_upload782111/files_33/ourdev_583022LP264J.jpg
(原文件名:P}6W9ESFWNEH{NUE7
我原先的是ISE9.2版的，那个Lock Pins是可以通过的，不知怎么这次就通不过了，那个错误研究了很长时间，但还是不知怎么改 回复【15楼】simplorer
-----------------------------------------------------------------------
问你个问题，今天我用ISE10.1的版本，
结果发现一个问题，也是可以下载，没有输出结果（用的一个简单的程序）
但发现一个问题，
http://cache.amobbs.com/bbs_upload782111/files_33/ourdev_583022LP264J.jpg
(原文件名:P}6W9ESFWNEH{NUE7
我原先的是ISE9.2版的，那个Lock Pins是可以通过的，不知怎么这次就通不过了，那个错误研究了很长时间，但还是不知怎么改 是不是复位脚的问题，不能悬空，按高低电平要求接好
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