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发表于 2010-9-12 22:04:47
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回复【7楼】ngzhang 兽哥
-----------------------------------------------------------------------
这是在FPGA中的综合报告
Release 9.2i - xst J.36
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.27 s | Elapsed : 0.00 / 1.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.27 s | Elapsed : 0.00 / 1.00 s
--> Reading design: sss.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "sss.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "sss"
Output Format : NGC
Target Device : xc3s400-5-pq208
---- Source Options
Top Module Name : sss
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : sss.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "sss.v" in library work
Module <sss> compiled
No errors in compilation
Analysis of file <"sss.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <sss> in library <work>.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <sss>.
Module <sss> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
INFO:Xst:2679 - Register <b2> in unit <sss> has a constant value of 0000011000111111 during circuit operation. The register is replaced by logic.
Synthesizing Unit <sss>.
Related source file is "sss.v".
Found 6-bit register for signal <pwm>.
Found 16-bit up counter for signal <cnt1>.
Found 16-bit comparator less for signal <pwm$cmp_lt0000> created at line 44.
Summary:
inferred 1 Counter(s).
inferred 6 D-type flip-flop(s).
inferred 1 Comparator(s).
Unit <sss> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Counters : 1
16-bit up counter : 1
# Registers : 1
6-bit register : 1
# Comparators : 1
16-bit comparator less : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Loading device for application Rf_Device from file '3s400.nph' in environment E:\Xilinx.
WARNING:Xst:1710 - FF/Latch <pwm_2> (without init value) has a constant value of 0 in block <sss>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pwm_3> (without init value) has a constant value of 0 in block <sss>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pwm_4> (without init value) has a constant value of 0 in block <sss>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pwm_5> (without init value) has a constant value of 0 in block <sss>.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Counters : 1
16-bit up counter : 1
# Registers : 2
Flip-Flops : 2
# Comparators : 1
16-bit comparator less : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <sss> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block sss, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 18
Flip-Flops : 18
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : sss.ngr
Top Level Output File Name : sss
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 8
Cell Usage :
# BELS : 73
# GND : 1
# INV : 4
# LUT1 : 16
# LUT2 : 3
# LUT3 : 1
# LUT4 : 6
# MUXCY : 26
# VCC : 1
# XORCY : 15
# FlipFlops/Latches : 18
# FDR : 17
# FDRS : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 7
# IBUF : 1
# OBUF : 6
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s400pq208-5
Number of Slices: 16 out of 3584 0%
Number of Slice Flip Flops: 18 out of 7168 0%
Number of 4 input LUTs: 30 out of 7168 0%
Number of IOs: 8
Number of bonded IOBs: 8 out of 141 5%
Number of GCLKs: 1 out of 8 12%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 18 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 6.314ns (Maximum Frequency: 158.373MHz)
Minimum input arrival time before clock: 6.181ns
Maximum output required time after clock: 6.216ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 6.314ns (frequency: 158.373MHz)
Total number of paths / destination ports: 424 / 34
-------------------------------------------------------------------------
Delay: 6.314ns (Levels of Logic = 7)
Source: cnt1_4 (FF)
Destination: cnt1_1 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: cnt1_4 to cnt1_1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 3 0.626 1.066 cnt1_4 (cnt1_4)
LUT1:I0->O 1 0.479 0.000 cnt1_and0000_wg_cy<0>_rt (cnt1_and0000_wg_cy<0>_rt)
MUXCY:S->O 1 0.435 0.000 cnt1_and0000_wg_cy<0> (cnt1_and0000_wg_cy<0>)
MUXCY:CI->O 1 0.056 0.000 cnt1_and0000_wg_cy<1> (cnt1_and0000_wg_cy<1>)
MUXCY:CI->O 1 0.056 0.000 cnt1_and0000_wg_cy<2> (cnt1_and0000_wg_cy<2>)
MUXCY:CI->O 1 0.056 0.000 cnt1_and0000_wg_cy<3> (cnt1_and0000_wg_cy<3>)
MUXCY:CI->O 2 0.246 0.915 cnt1_and0000_wg_cy<4> (cnt1_and0000)
LUT2:I1->O 15 0.479 1.010 Mcount_cnt1_val1 (Mcount_cnt1_val)
FDR:R 0.892 cnt1_1
----------------------------------------
Total 6.314ns (3.323ns logic, 2.991ns route)
(52.6% logic, 47.4% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 34 / 19
-------------------------------------------------------------------------
Offset: 6.181ns (Levels of Logic = 4)
Source: rst (PAD)
Destination: cnt1_1 (FF)
Destination Clock: clk rising
Data Path: rst to cnt1_1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 3 0.715 1.066 rst_IBUF (rst_IBUF)
LUT4:I0->O 1 0.479 0.000 cnt1_and0000_wg_lut<4> (N3)
MUXCY:S->O 2 0.625 0.915 cnt1_and0000_wg_cy<4> (cnt1_and0000)
LUT2:I1->O 15 0.479 1.010 Mcount_cnt1_val1 (Mcount_cnt1_val)
FDR:R 0.892 cnt1_1
----------------------------------------
Total 6.181ns (3.190ns logic, 2.991ns route)
(51.6% logic, 48.4% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 6.216ns (Levels of Logic = 1)
Source: pwm_1 (FF)
Destination: pwm<1> (PAD)
Source Clock: clk rising
Data Path: pwm_1 to pwm<1>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 1 0.626 0.681 pwm_1 (pwm_1)
OBUF:I->O 4.909 pwm_1_OBUF (pwm<1>)
----------------------------------------
Total 6.216ns (5.535ns logic, 0.681ns route)
(89.0% logic, 11.0% route)
=========================================================================
CPU : 4.72 / 5.09 s | Elapsed : 4.00 / 5.00 s
-->
Total memory usage is 139752 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 4 ( 0 filtered)
Number of infos : 1 ( 0 filtered) |
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发表于 2010-9-12 20:11:00
