在FPGA中进行组合逻辑运算,如何消除静态冒险
大家好,我有个项目问题很棘手。当在FPGA中进行组合逻辑运算时,由于逻辑之间的门延迟不同,导致输出结果会产生毛刺,即为静态冒险。书上说用卡诺图来解决,但是在FPGA中怎么解决呢?
小弟请教大家,我把图传上来,如何能够消除这些毛刺?
万分感谢!
http://cache.amobbs.com/bbs_upload782111/files_32/ourdev_577970.JPG
有很多寄存器和输出信号有毛刺 (原文件名:11.JPG) 用时钟打,不过如果你的逻辑输出不是接下级的时钟,有毛刺也没有问题 回复【1楼】888888888888
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您的意思是说只要组合逻辑的输出不是作为下级的时钟信号就可以吗? 组合逻辑程序,麻烦大家
//----------------------------------------------------------------------------------
always @(trig or not_ctr_fir or gate_ctr)
begin
choose_signal(trig, not_ctr_fir, gate_ctr, out_sec_1);
choose_signal(trig, not_ctr_fir, gate_ctr, out_sec_1);
choose_signal(trig, not_ctr_fir, gate_ctr, out_sec_1);
choose_signal(trig, not_ctr_fir, gate_ctr, out_sec_1);
choose_signal(trig, not_ctr_fir, gate_ctr, out_sec_1);
choose_signal(trig, not_ctr_fir, gate_ctr, out_sec_1);
out_thi_1 = & out_sec_1;
choose_signal(trig, not_ctr_fir, gate_ctr, out_sec_2);
choose_signal(trig, not_ctr_fir, gate_ctr, out_sec_2);
choose_signal(trig, not_ctr_fir, gate_ctr, out_sec_2);
choose_signal(trig, not_ctr_fir, gate_ctr, out_sec_2);
choose_signal(trig, not_ctr_fir, gate_ctr, out_sec_2);
choose_signal(trig, not_ctr_fir, gate_ctr, out_sec_2);
out_thi_2 = & out_sec_2;
choose_signal(trig, not_ctr_fir, gate_ctr, out_sec_3);
choose_signal(trig, not_ctr_fir, gate_ctr, out_sec_3);
choose_signal(trig, not_ctr_fir, gate_ctr, out_sec_3);
choose_signal(trig, not_ctr_fir, gate_ctr, out_sec_3);
choose_signal(trig, not_ctr_fir, gate_ctr, out_sec_3);
choose_signal(trig, not_ctr_fir, gate_ctr, out_sec_3);
out_fou_3 = & out_sec_3;
end
//----------------------------------------------------------------------------------
//---------------------------------------------------
//task
task choose_signal;
input trig_r;
input not_ctr_fir_r;
input gate_ctr_r;
output out_sec_r;
if(not_ctr_fir_r)
begin
if(gate_ctr_r) out_sec_r = ~trig_r;
else out_sec_r = 1'b1;
end
else
begin
if(gate_ctr_r) out_sec_r = trig_r;
else out_sec_r = 1'b1;
end
endtask
//---------------------------------------------------
always @(out_thi_1 or not_ctr_sec)
if(not_ctr_sec) out_fou_1 = ~out_thi_1;
else out_fou_1 = out_thi_1;
always @(out_thi_2 or not_ctr_sec)
if(not_ctr_sec) out_fou_2 = ~out_thi_2;
else out_fou_2 = out_thi_2;
always @(not_ctr_third or out_fou_1 or out_fou_2 or out_fou_3)
if(not_ctr_third) out_logic = ~(out_fou_1 & out_fou_2 & out_fou_3);
else out_logic = out_fou_1 & out_fou_2 & out_fou_3;
应该是门延时造成的,请问应该怎么办?难道用时序逻辑来做吗? 在fpga中要坚持时序逻辑设计。等信号稳定以后再用沿采样。
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