Verilog 优化代码问题。
代码如下case( EB_A )
EBCMD_X:
begin
if( r_cmd_xyhl==XYHL_STA )
begin
r_cmd_x = EB_D;
r_cmd_xyhl = XYHL_END;
end
else
begin
r_cmd_x = EB_D;
r_cmd_xyhl = XYHL_STA;
r_cmd_addr = r_cmd_x+r_cmd_y*10'd800;
r_rw_addr_sta = CMD_CALC_ADDR;
end
end
EBCMD_Y:
begin
if( r_cmd_xyhl==XYHL_STA )
begin
r_cmd_y = EB_D;
r_cmd_xyhl = XYHL_END;
end
else
begin
r_cmd_y = EB_D;
r_cmd_xyhl = XYHL_STA;
r_cmd_addr = r_cmd_x+r_cmd_y*10'd800;
r_rw_addr_sta = CMD_CALC_ADDR;
end
end
代码中使用了2次r_cmd_addr = r_cmd_x+r_cmd_y*10'd800; 会占用2个乘法器资源,能否有好的办法优化呢? 据说乘以一个常数可以用移位来代替x*800=x<<9+x<<8+x<<5;
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