yl604922959 发表于 2010-8-3 15:24:01

ise 里的1706到底是什么错误啊?

以下是产生错误的代码,不是最开始的了,因为我按着ise的注释改了半天了,里面存在一些有点冗余的reg
但是编译以后总是产生1706错误,一会我把报告也贴上来
module ad_all(clk,wr,data,datain,test,data0,data1,data2,data3);

input clk;
input datain;
output wr;
output data;
output test;
output data0,data1,data2,data3;
reg data1,data2,data3;
reg data0;

reg te0,te1,te2,te3;
reg cnt,cnttemp;
reg data;
reg        temp;
reg test;
reg wr;
reg ok;
reg tempx;

always @(posedge clk)
begin
        test<=1'b0;
        ok<=1'b1;
        data0<=16'h0107;
        tempx=16'h0102;
begin
       
        temp<=datain;
        if(temp)
        begin
               
                begin
                        ok<=1'b0;
                        if(temp>32'd4096)
                        begin
                                temp<=temp-32'd4096;
                               
                               
                        end
                        else if(32'd4096>temp>=32'd1000)
                        begin
                                temp<=temp-32'd1000;
                                te0<=te0+32'd1;
                        end
                        else if(32'd1000>temp>=32'd100)
                        begin
                                temp<=temp-32'd100;
                                te1<=te1+32'd1;
                        end
                        else if(32'd100>temp>=32'd10)
                        begin
                                temp<=temp-32'd10;
                                te2<=te2+32'd1;
                        end
                        else
                        begin
                               
                                data0<=te0;
                                data1<=te1;
                                data2<=te2;
                                te3<=temp;
                                data3<=te3;
                                //ok<=1'b1;
                                data0<=8'h01;
                                data1<=8'h02;
                                data2<=8'h03;
                                data3<=8'h04;
                                test<=1'b1;
                        end
                end
        end
       
if(ok)
begin
//test<=1'b1;       
wr<=1'b0;
tempx=8'h01;
tempx=8'h02;
        if(cnt==16'd1)
        begin
                wr<=1'b1;
                cnt<=cnt+16'd1;
               
                if(cnttemp==16'd13)
                begin
                        cnttemp <= 0;
                end                       
                else
                begin
                        case (cnttemp)
                        16'd0:        data <= 16'h0a07;
                        16'd1:        data <= 16'h0b07;
                        16'd2:        data <= 16'h0c01;
                        16'd3:        data <= 16'h09ff;
                        16'd4:        data <= 16'h0f00;
                        /*
                        16'd5:        begin data<=16'h01ff;data<={data,(data0&&data)};end
                        16'd6:        begin data<=16'h02ff;data<={data,(data1&&data)};end
                        16'd7:        begin data<=16'h03ff;data<={data,(data2&&data)};end
                        16'd8:        begin data<=16'h04ff;data<={data,(data3&&data)};end
                        16'd9:        begin data<= 16'h0504;temp<=temp+8'd1;data<=(data&temp);end
                        */
                       
                        16'd5:        data <=tempx;
                        16'd6:        data <= 16'h0206;
                        16'd7:        data <= 16'h0306;
                        16'd8:        data <= 16'h0406;
                       
                        /*
                        16'd5:        data <= data0;
                        16'd6:        data <= data1;
                        16'd7:        data <= data2;
                        16'd8:        data <= data3;
                        */
                        16'd9:        data <= 16'h0506;
                        16'd10:        data <= 16'h0605;
                        16'd11:        data <= 16'h0706;
                        16'd12:        data <= 16'h0807;
                        default: data <= 16'h0000;
                        endcase       
                        cnttemp <= cnttemp +1;
                end               
        end
       
        else if(cnt==16'd60)
        begin
                wr<=1'b0;
                cnt<=16'd0;
        end
       
        else
        begin
                cnt<=cnt+16'd1;
        end
end
end       
end
endmodule

yl604922959 发表于 2010-8-3 15:24:58

Synthesis Messages 星期二 八月 3 15:25:21 2010

--------------------------------------------------------------------------------

Synthesis Messages - Errors, Warnings, and Infos New
WARNING Xst:2211 - "./mul.v" line 269: Instantiating black box module <mul>.

WARNING Xst:2211 - "count_ud_8.v" line 473: Instantiating black box module <count_ud_8>.

WARNING Xst:2211 - "count_ud_8.v" line 482: Instantiating black box module <count_ud_8>.

WARNING Xst:852 - "pwm_gen1.vf" line 503: Unconnected input port 'CI' of instance 'XLXI_74' is tied to GND.

WARNING Xst:2211 - "count_ud_8.v" line 510: Instantiating black box module <count_ud_8>.

INFO Xst:2679 - Register <dataout> in unit <spi_ad_controller> has a constant value of 0000100000110001 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <tempx<15>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <tempx<14>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <tempx<13>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <tempx<12>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <tempx<11>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <tempx<10>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <tempx<9>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <tempx<8>> in unit <ad_all> has a constant value of 1 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <tempx<7>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <tempx<6>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <tempx<5>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <tempx<4>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <tempx<3>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <tempx<2>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <tempx<1>> in unit <ad_all> has a constant value of 1 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <tempx<0>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data0<15>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data0<14>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data0<13>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data0<12>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data0<11>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data0<10>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data0<9>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data0<8>> in unit <ad_all> has a constant value of 1 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data1<15>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data1<14>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data1<13>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data1<12>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data1<11>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data1<10>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data1<9>> in unit <ad_all> has a constant value of 1 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data1<8>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data2<15>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data2<14>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data2<13>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data2<12>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data2<11>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data2<10>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data2<9>> in unit <ad_all> has a constant value of 1 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data2<8>> in unit <ad_all> has a constant value of 1 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data3<15>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data3<14>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data3<13>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data3<12>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data3<11>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data3<10>> in unit <ad_all> has a constant value of 1 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data3<9>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

INFO Xst:2679 - Register <data3<8>> in unit <ad_all> has a constant value of 0 during circuit operation. The register is replaced by logic.

WARNING Xst:646 - Signal <tempx> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

WARNING Xst:653 - Signal <dummy> is used but never assigned. This sourceless signal will be automatically connected to value 0.

WARNING Xst:1306 - Output <dataout> is never assigned.

WARNING Xst:1780 - Signal <tpp19> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

WARNING Xst:653 - Signal <XLXN_416> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.

WARNING Xst:653 - Signal <XLXN_307> is used but never assigned. This sourceless signal will be automatically connected to value 0.

WARNING Xst:646 - Signal <XLXN_265> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

WARNING Xst:646 - Signal <XLXN_264> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

WARNING Xst:646 - Signal <XLXN_263> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

WARNING Xst:646 - Signal <XLXN_173> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

INFO Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

WARNING Xst:1709 - Edge <data2_7_index0000>, from block <ad_all>, has no source

WARNING Xst:1709 - Edge <data1_7_index0000>, from block <ad_all>, has no source

WARNING Xst:1709 - Edge <data0_7_index0000>, from block <ad_all>, has no source

WARNING Xst:2677 - Node <out_data_0> of sequential type is unconnected in block <XLXI_193>.

WARNING Xst:2677 - Node <out_data_1> of sequential type is unconnected in block <XLXI_193>.

WARNING Xst:2677 - Node <out_data_2> of sequential type is unconnected in block <XLXI_193>.

WARNING Xst:2677 - Node <out_data_3> of sequential type is unconnected in block <XLXI_193>.

WARNING Xst:2677 - Node <out_data_4> of sequential type is unconnected in block <XLXI_193>.

WARNING Xst:2677 - Node <out_data_5> of sequential type is unconnected in block <XLXI_193>.

WARNING Xst:2677 - Node <out_data_6> of sequential type is unconnected in block <XLXI_193>.

WARNING Xst:2677 - Node <out_data_7> of sequential type is unconnected in block <XLXI_193>.

WARNING Xst:2677 - Node <out_data_8> of sequential type is unconnected in block <XLXI_193>.

WARNING Xst:2677 - Node <out_data_9> of sequential type is unconnected in block <XLXI_193>.

WARNING Xst:2677 - Node <out_data_10> of sequential type is unconnected in block <XLXI_193>.

WARNING Xst:2677 - Node <out_data_11> of sequential type is unconnected in block <XLXI_193>.

WARNING Xst:2677 - Node <out_data_12> of sequential type is unconnected in block <XLXI_193>.

WARNING Xst:2677 - Node <out_data_13> of sequential type is unconnected in block <XLXI_193>.

WARNING Xst:2677 - Node <out_data_14> of sequential type is unconnected in block <XLXI_193>.

WARNING Xst:2677 - Node <out_data_15> of sequential type is unconnected in block <XLXI_193>.

WARNING Xst:2677 - Node <data0_7> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data0_4> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data0_6> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data0_5> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data0_1> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data0_3> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data0_2> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data1_7> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data0_0> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data1_4> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data1_6> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data1_5> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data1_1> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data1_3> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data1_2> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data2_6> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data1_0> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data2_7> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data2_5> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data2_4> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data2_1> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data2_3> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data2_2> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data2_0> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <te3_0> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <te3_1> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <te3_2> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <te3_3> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <te3_4> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <te3_5> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <te3_6> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <te3_7> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data3_7> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data3_4> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data3_6> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data3_5> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data3_3> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data3_2> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data3_1> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:2677 - Node <data3_0> of sequential type is unconnected in block <XLXI_217>.

WARNING Xst:1710 - FF/Latch <data_12> (without init value) has a constant value of 0 in block <ad_all>. This FF/Latch will be trimmed during the optimization process.

WARNING Xst:1895 - Due to other FF/Latch trimming, FF/Latch <data_13> (without init value) has a constant value of 0 in block <ad_all>. This FF/Latch will be trimmed during the optimization process.

WARNING Xst:1895 - Due to other FF/Latch trimming, FF/Latch <data_14> (without init value) has a constant value of 0 in block <ad_all>. This FF/Latch will be trimmed during the optimization process.

WARNING Xst:1895 - Due to other FF/Latch trimming, FF/Latch <data_15> (without init value) has a constant value of 0 in block <ad_all>. This FF/Latch will be trimmed during the optimization process.

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data0_4> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data0_6> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data0_5> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data0_1> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data0_3> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data0_2> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data0_0> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data1_4> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data1_6> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data1_5> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data1_1> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data1_3> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data1_2> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data2_6> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data1_0> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data2_5> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data2_4> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data2_1> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data2_3> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data2_2> has no source

ERROR Xst:1706 - Unit <ad_all>: port <D> of FF/Latch <data2_0> has no source

ERROR Xst:1847 - Design checking failed

</t

liquanmin 发表于 2011-3-10 21:14:06

回复【1楼】yl604922959 tear
-----------------------------------------------------------------------

不知楼主这个问题解决了吗?我也遇到了同样的问题,不知该怎么办.可否指教?

yl604922959 发表于 2011-8-26 10:21:42

很久以前就解决了,是ise自己的优化问题

wenjing103 发表于 2012-9-20 21:08:38

yl604922959 发表于 2011-8-26 10:21 static/image/common/back.gif
很久以前就解决了,是ise自己的优化问题

敢问大侠,到底该如何解决啊????
页: [1]
查看完整版本: ise 里的1706到底是什么错误啊?