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以下是产生错误的代码，不是最开始的了，因为我按着ise的注释改了半天了，里面存在一些有点冗余的reg
但是编译以后总是产生1706错误，一会我把报告也贴上来
module ad_all(clk,wr,data,datain,test,data0,data1,data2,data3);
input clk;
input [31:0] datain;
output wr;
output [15:0] data;
output test;
output [15:0] data0,data1,data2,data3;
reg [15:0] data1,data2,data3;
reg [15:0] data0;
reg [7:0] te0,te1,te2,te3;
reg [15:0] cnt,cnttemp;
reg [15:0] data;
reg [31:0] temp;
reg test;
reg wr;
reg ok;
reg [15:0] tempx;
always @(posedge clk)
begin
test<=1'b0;
ok<=1'b1;
data0<=16'h0107;
tempx=16'h0102;
begin
temp<=datain;
if(temp)
begin
begin
ok<=1'b0;
if(temp>32'd4096)
begin
temp<=temp-32'd4096;
end
else if(32'd4096>temp>=32'd1000)
begin
temp<=temp-32'd1000;
te0<=te0+32'd1;
end
else if(32'd1000>temp>=32'd100)
begin
temp<=temp-32'd100;
te1<=te1+32'd1;
end
else if(32'd100>temp>=32'd10)
begin
temp<=temp-32'd10;
te2<=te2+32'd1;
end
else
begin
data0[7:0]<=te0[7:0];
data1[7:0]<=te1[7:0];
data2[7:0]<=te2[7:0];
te3[7:0]<=temp[7:0];
data3[7:0]<=te3[7:0];
//ok<=1'b1;
data0[15:8]<=8'h01;
data1[15:8]<=8'h02;
data2[15:8]<=8'h03;
data3[15:8]<=8'h04;
test<=1'b1;
end
end
end
if(ok)
begin
//test<=1'b1;
wr<=1'b0;
tempx[15:8]=8'h01;
tempx[7:0]=8'h02;
if(cnt==16'd1)
begin
wr<=1'b1;
cnt<=cnt+16'd1;
if(cnttemp==16'd13)
begin
cnttemp <= 0;
end
else
begin
case (cnttemp)
16'd0: data <= 16'h0a07;
16'd1: data <= 16'h0b07;
16'd2: data <= 16'h0c01;
16'd3: data <= 16'h09ff;
16'd4: data <= 16'h0f00;
/*
16'd5: begin data<=16'h01ff;data<={data[15:8],(data0&&data[7:0])};end
16'd6: begin data<=16'h02ff;data<={data[15:8],(data1&&data[7:0])};end
16'd7: begin data<=16'h03ff;data<={data[15:8],(data2&&data[7:0])};end
16'd8: begin data<=16'h04ff;data<={data[15:8],(data3&&data[7:0])};end
16'd9: begin data<= 16'h0504;temp<=temp+8'd1;data<=(data&temp);end
*/
16'd5: data <=tempx;
16'd6: data <= 16'h0206;
16'd7: data <= 16'h0306;
16'd8: data <= 16'h0406;
/*
16'd5: data <= data0;
16'd6: data <= data1;
16'd7: data <= data2;
16'd8: data <= data3;
*/
16'd9: data <= 16'h0506;
16'd10: data <= 16'h0605;
16'd11: data <= 16'h0706;
16'd12: data <= 16'h0807;
default: data <= 16'h0000;
endcase
cnttemp <= cnttemp +1;
end
end
else if(cnt==16'd60)
begin
wr<=1'b0;
cnt<=16'd0;
end
else
begin
cnt<=cnt+16'd1;
end
end
end
end
endmodule |
阿莫论坛20周年了！感谢大家的支持与爱护！！
知道什么是神吗？其实神本来也是人，只不过神做了人做不到的事情 所以才成了神。 （头文字D, 杜汶泽）
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发表于 2010-8-3 15:24:01
楼主
