新手请教inout类型仿真结果全是XXX问题
刚接触FPGA,学习inout类型,写了存储器小程序仿真,可是全是XXX,请大家赐教...储存器代码如下:
module myRAM(IN,OUT,EN,DATA,ADDR);
input IN,OUT,EN;
input ADDR;
inout DATA;
reg DATABUF;
reg MEM;
wire DATA;
assign DATA = DATABUF;
always @(posedge IN or posedge OUT)
begin
if(!EN)
DATABUF = 8'bzzzzzzzz;
else
if((IN==1)&&(OUT==0))
MEM = DATA;
else
if((IN==0)&&(OUT==1))
DATABUF = MEM;
else
DATABUF = 8'bzzzzzzzz;
end
endmodule
测试代码如下:
`timescale 1ns/1ns
`include "myRAM.v"
module myRAM_TB;
reg in_ctr,out_ctr,en_ctr;
reg addr_bus,data_buf;
wire data_bus;
integer i;
myRAM mytest(.IN(in_ctr),.OUT(out_ctr),.EN(en_ctr),.DATA(data_bus),.ADDR(addr_bus));
assign data_bus = data_buf;
initial
begin
en_ctr = 0;
#50 en_ctr = 1;
out_ctr = 0;
for(i=0;i<256;i=i+1)
begin
#10 in_ctr = 0;
addr_bus = i;
data_buf = i;
#10 in_ctr = 1;
end
i = 0;
in_ctr = 0;
while(1)
begin
#10 out_ctr = 0;
addr_bus = i;
#10 out_ctr = 1;
i = i + 1;
end
end
endmodule http://cache.amobbs.com/bbs_upload782111/files_30/ourdev_563354KFFFBF.png
(原文件名:QQ截图未命名2.png) http://cache.amobbs.com/bbs_upload782111/files_30/ourdev_563355ARQEIK.png
(原文件名:QQ截图未命名.png) 顶啊,走过路过的朋友,看看怎么回事啊?坛子里类似的问题都没个结果,希望能顶出个结果来! 三态信号要声明成上拉。 回复【4楼】ngzhang 兽哥
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谢谢 ngzhang 兽哥,我修改了下程序,输入正常了,输出还是不对...低电平是X,高电平是1,不知道怎么回事.... module myRAM(IN,OUT,EN,DATA,ADDR);
input IN,OUT,EN;
input ADDR;
inout DATA;
reg DATABUF;
reg MEM;
tri1 DATA;
assign DATA = ((OUT==1)&&(IN==0))?DATABUF:8'bzzzzzzzz;
always @(posedge EN)
begin
if((IN==1)&&(OUT==0))
MEM = DATA;
else
if((OUT==1)&&(IN==0))
DATABUF = MEM;
else
DATABUF = 8'b0;
end
endmodule http://cache.amobbs.com/bbs_upload782111/files_30/ourdev_564553BA0NS4.JPG
(原文件名:波形.JPG) 好像还有信号驱动强度的问题,搜索一下。具体的我忘了。 回复【8楼】ngzhang 兽哥
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谢谢!主要是没这方面的例程,现在完全是照着书本,加上自己的想象乱搞modelsim...,等几天买个板子回来看看有例程没,搞定的话把结果发上来 楼主最后怎么解决的呢 我的是0 是对1全是x inout在写TB时会自动生成wire线,必须手工指定三态或EN。
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