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刚接触FPGA,学习inout类型,写了存储器小程序仿真,可是全是XXX,请大家赐教...
储存器代码如下:
module myRAM(IN,OUT,EN,DATA,ADDR);
input IN,OUT,EN;
input [7:0] ADDR;
inout [7:0] DATA;
reg [7:0] DATABUF;
reg [7:0] MEM[255:0];
wire [7:0] DATA;
assign DATA = DATABUF;
always @(posedge IN or posedge OUT)
begin
if(!EN)
DATABUF = 8'bzzzzzzzz;
else
if((IN==1)&&(OUT==0))
MEM[ADDR] = DATA;
else
if((IN==0)&&(OUT==1))
DATABUF = MEM[ADDR];
else
DATABUF = 8'bzzzzzzzz;
end
endmodule
测试代码如下:
`timescale 1ns/1ns
`include "myRAM.v"
module myRAM_TB;
reg in_ctr,out_ctr,en_ctr;
reg [7:0] addr_bus,data_buf;
wire [7:0] data_bus;
integer i;
myRAM mytest(.IN(in_ctr),.OUT(out_ctr),.EN(en_ctr),.DATA(data_bus),.ADDR(addr_bus));
assign data_bus = data_buf;
initial
begin
en_ctr = 0;
#50 en_ctr = 1;
out_ctr = 0;
for(i=0;i<256;i=i+1)
begin
#10 in_ctr = 0;
addr_bus = i;
data_buf = i;
#10 in_ctr = 1;
end
i = 0;
in_ctr = 0;
while(1)
begin
#10 out_ctr = 0;
addr_bus = i;
#10 out_ctr = 1;
i = i + 1;
end
end
endmodule |
阿莫论坛20周年了!感谢大家的支持与爱护!!
知道什么是神吗?其实神本来也是人,只不过神做了人做不到的事情 所以才成了神。 (头文字D, 杜汶泽)
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