编译出错，请高手指教
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity control_module is
port(
wclk :instd_logic;
rclk :instd_logic;
wr_en:instd_logic;
ce_1 :outstd_logic;
ce_2 :outstd_logic;
rce_1 :outstd_logic;
rce_2 :outstd_logic);
endcontrol_module ;
architecture Behavioral ofcontrol_moduleis
signal wr_flag:std_logic_vector(10 downto 0):="00000000000";
signal rd_flag:std_logic_vector(10 downto 0):="00000000000";
signal ce1_reg:std_logic:='1';
signal ce2_reg:std_logic:='0';
signal rce1_reg :std_logic:='0';
signal rce2_reg :std_logic:='1';
begin
p1:process(wclk,rclk,wr_en)
begin
if(wr_en='1') then
if rising_edge(wclk) then
wr_flag(10 downto 0)<=wr_flag(10 downto 0)+1;
if rising_edge(rclk) then
rd_flag(10 downto 0)<=rd_flag(10 downto 0)+1;
if wr_flag(10 downto 0)="01111111111" then
if rd_flag(10 downto 0)="01111111111" then
rce1_reg<='1';
rce2_reg<='0';
rce_1<=rce1_reg;
rce_2<=rce2_reg;
ce1_reg<='0';
ce2_reg<='1';
ce_1<=ce1_reg;
ce_2<=ce2_reg;
elsif wr_flag(10 downto 0)="11111111111" then
if rd_flag(10 downto 0)="11111111111" then
rce1_reg<='0';
rce2_reg<='1';
rce_1<=rce1_reg;
rce_2<=rce2_reg;
ce1_reg<='1';
ce2_reg<='0';
ce_1<=ce1_reg;
ce_2<=ce2_reg;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
p2:process(wclk,rclk,wr_en)
begin
if(wr_en='1') then
if rising_edge(wclk) then
wr_flag(10 downto 0)<=wr_flag(10 downto 0)+1;
if rising_edge(rclk) then
rd_flag(10 downto 0)<=rd_flag(10 downto 0)+1;
if wr_flag(9 downto 0)= "1111111111" then
if rd_flag(9 downto 0)/="1111111111" then
ce1_reg<='0';
ce2_reg<='0';
ce_1<=ce1_reg;
ce_2<=ce2_reg;
end if;
end if;
end if;
end if;
end if;
end process;
endBehavioral;
Error (10821): HDL error at control_module.vhd(65): can't infer register for "ce_2" because its behavior does not match any supported register model
Error (10821): HDL error at control_module.vhd(65): can't infer register for "ce_1" because its behavior does not match any supported register model
Error (10821): HDL error at control_module.vhd(65): can't infer register for "ce2_reg" because its behavior does not match any supported register model
Error (10821): HDL error at control_module.vhd(65): can't infer register for "ce1_reg" because its behavior does not match any supported register model
Error (10821): HDL error at control_module.vhd(65): can't infer register for "rd_flag" because its behavior does not match any supported register model
Error (10821): HDL error at control_module.vhd(65): can't infer register for "rd_flag" because its behavior does not match any supported register model
Error (10821): HDL error at control_module.vhd(65): can't infer register for "rd_flag" because its behavior does not match any supported register model
Error (10821): HDL error at control_module.vhd(65): can't infer register for "rd_flag" because its behavior does not match any supported register model
Error (10821): HDL error at control_module.vhd(65): can't infer register for "rd_flag" because its behavior does not match any supported register model
Error (10821): HDL error at control_module.vhd(65): can't infer register for "rd_flag" because its behavior does not match any supported register model
Error (10821): HDL error at control_module.vhd(65): can't infer register for "rd_flag" because its behavior does not match any supported register model
Error (10821): HDL error at control_module.vhd(65): can't infer register for "rd_flag" because its behavior does not match any supported register model
Error (10821): HDL error at control_module.vhd(65): can't infer register for "rd_flag" because its behavior does not match any supported register model
Error (10821): HDL error at control_module.vhd(65): can't infer register for "rd_flag" because its behavior does not match any supported register model rd_flag(10 downto 0)+1;
这个不能直接加1吧? 顶 同问 后来 怎么改的
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