这个程序为什么编译不通过呢？？
module segment(clk,
rst_n,
sw0,
sw1,
sw2,
sw3,
//output
hc_cp,
hc_si
);
input clk;
input rst_n;
input sw0,sw1,sw2,sw3; //Active low
outputhc_cp;
outputhc_si;
reg data;
integer count;
integer shuaxin;
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)begin
count <= 0;
data <= 4'h0;
end
else begin
if(count==16_000_000)begin
count<=0;
data <= data + 1'b1;
end
else begin
count <= count +1'b1;
end
end
end
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)begin
shuaxin<=0;
end
else begin
if(shuaxin==5000)begin
shuaxin<=0;
hc164_driver hc164_driver_inst(
.clk ( clk ),
.rst_n ( rst_n ),
.led ( 0 ),
.dot ( 0 ),
.seg_value ( {4'd1,data,4'd2,4'd3} ),
.hc_cp ( hc_cp ),
.hc_si ( hc_si )
);
end
else
shuaxin<=shuaxin + 1'b1;
end
end
endmodule
// hc164_driver模块
module hc164_driver(
clk,rst_n, led, dot, seg_value, hc_cp, hc_si );
input clk;
input rst_n;
input led;
input dot;
input seg_value;
outputreg hc_cp; //HC164 Clock input active Rising edges
output hc_si; //HC164 Data input
reg tx_cnt;
reg hex2led; //hex-to-seven-segment decoder output
reg hc_data_34bit;
reg hc_data_31bit;
wirehc_data = {led,hc_data_34bit,hex2led,hc_data_31bit, hex2led};
wirehc_data_inv = { hc_data,
hc_data,hc_data,hc_data, hc_data,
hc_data,hc_data,hc_data, hc_data,
hc_data,hc_data,hc_data, hc_data,
hc_data, hc_data, hc_data};
reg clk_cnt;
always @ ( posedge clk or negedge rst_n )
if ( !rst_n ) clk_cnt <= 16'd0;
elseclk_cnt <= clk_cnt + 1'b1;
reg seg_led_num;
always @ ( posedge clk or negedge rst_n )
if (!rst_n ) seg_led_num <= 2'b00;
else if ( clk_cnt == 16'hFFFF ) seg_led_num <= seg_led_num + 1'b1;
reg hex;
always @ ( * )
case ( seg_led_num )
2'b00: hex = seg_value;
2'b01: hex = seg_value;
2'b10: hex = seg_value;
2'b11: hex = seg_value;
endcase
always @ ( * )
begin
case (hex) //数值
4'h1: hex2led = 7'b0010_100; //1
4'h2: hex2led = 7'b1011_011; //2
4'h3: hex2led = 7'b1011_110; //3
4'h4: hex2led = 7'b0111_100; //4
4'h5: hex2led = 7'b1101_110; //5
4'h6: hex2led = 7'b1101_111; //6
4'h7: hex2led = 7'b1010_100; //7
4'h8: hex2led = 7'b1111_111; //8
4'h9: hex2led = 7'b1111_100; //9
4'hA: hex2led = 7'b1111_101; //A
4'hB: hex2led = 7'b0101_111; //b
4'hC: hex2led = 7'b1100_011; //C
4'hD: hex2led = 7'b0011_111; //d
4'hE: hex2led = 7'b1101_011; //E
4'hF: hex2led = 7'b1101_001; //F
default : hex2led = 7'b1110_111; //0
endcase
end
always @ ( * )
case ( seg_led_num )
2'b00:hc_data_34bit = 4'b0111;
2'b01:hc_data_34bit = 4'b1011;
2'b10:hc_data_34bit = 4'b1101;
2'b11:hc_data_34bit = 4'b1110;
endcase
always @ ( * )
case ( seg_led_num )
2'b00:hc_data_31bit = dot;
2'b01:hc_data_31bit = dot;
2'b10:hc_data_31bit = dot;
2'b11:hc_data_31bit = dot;
endcase
always @ ( posedge clk or negedge rst_n )
if (!rst_n ) tx_cnt <= 6'd0;
else if ( clk_cnt ) tx_cnt <= 6'd0;
else if ((!clk_cnt) && (tx_cnt <= 6'd32 )) tx_cnt <= tx_cnt + 1'b1;
always @ ( posedge clk or negedge rst_n )
if (!rst_n)hc_cp <= 1'b0;
else if ( clk_cnt ) hc_cp <= 1'b0;
else if ((!clk_cnt) && (tx_cnt < 6'd32 )) hc_cp <= !hc_cp;
assignhc_si = hc_data_inv];
endmodule Error (10170): Verilog HDL syntax error at segment.v(45) near text "hc164_driver_inst";expecting "<=", or "="
我把下面这个放到最后就通过了，初学，请大家指教
hc164_driver hc164_driver_inst(
.clk ( clk ),
.rst_n ( rst_n ),
.led ( 0 ),
.dot ( 0 ),
.seg_value ( {4'd1,data,4'd2,4'd3} ),
.hc_cp ( hc_cp ),
.hc_si ( hc_si )
);
页:
[1]