清大家帮帮看看，怎么样jiejeu这个警告！
entity CLKDIV is------------------------------------------
port (
CLK_IN : instd_logic;
CLK_RST: instd_logic;
CLK_CS : instd_logic;
CLK_NUM: instd_logic_vector ( 8 downto 0 );
CLK_OUT: out std_logic
);
------------------------------------------
end CLKDIV;
architecture Behavioral of CLKDIV is
------------------------------------------
signal CLK_CLK: std_logic;
signal CLK_CNT: std_logic_vector ( 8 downto 0 );
------------------------------------------
begin
------------------------------------------
div:process ( CLK_RST,CLK_IN,CLK_CS )
begin
if ( CLK_RST = '0' ) then
CLK_CLK <= '1';
CLK_CNT <= "000000000";
elsif ( CLK_IN' event and CLK_IN = '1' and CLK_CS = '0' ) then
CLK_CNT <= CLK_CNT + 1;
if ( CLK_CNT = CLK_NUM ) then
CLK_CLK <= not CLK_CLK;
CLK_CNT <= "000000000";
end if;
end if;
end process div;
CLK_OUT <= CLK_CLK;
------------------------------------------
end Behavioral;
entity IIC_CLK is
------------------------------------------
port (
IIC_CLKIN: instd_logic;
IIC_RST: instd_logic;
IIC_CS: instd_logic;
IIC_CLKOUT0: out std_logic;
IIC_CLKOUT1: out std_logic
);
------------------------------------------
end IIC_CLK;
architecture Behavioral of IIC_CLK is
------------------------------------------
component CLKDIV
port (
CLK_IN : instd_logic;
CLK_RST: instd_logic;
CLK_CS : instd_logic;
CLK_NUM: instd_logic_vector ( 8 downto 0 );
CLK_OUT: out std_logic
);
end component;
------------------------------------------
------------------------------------------
signal IICaaaaSampClk: std_logic;
signal IICaaaaClk: std_logic;
signal IICDivNum0: std_logic_vector ( 8 downto 0 );
signal IICDivNum1: std_logic_vector ( 8 downto 0 );
------------------------------------------
begin
IICDivNum0 <= "000000000";
IICDivNum1 <= "000000000";
IIC_CLKOUT0 <= IICaaaaSampClk;
IIC_CLKOUT1 <= IICaaaaClk;
I2C_SampClk: CLKDIV
port map (
CLK_IN=> IIC_CLKIN,
CLK_RST => IIC_RST,
CLK_CS=> IIC_CS,
CLK_NUM => IICDivNum0,
CLK_OUT => IICaaaaSampClk
);
IIC_Clk: CLKDIV
port map (
CLK_IN=> IIC_CLKIN,
CLK_RST => IIC_RST,
CLK_CS=> IIC_CS,
CLK_NUM => IICDivNum1,
CLK_OUT => IICaaaaClk
);
end Behavioral; 我的开发环境是 ise10.1
编译出现下面的警告！不知道怎么解决！
WARNING:Xst:1989 - Unit <IIC_CLK>: instances <I2C_SampClk>, <IIC_Clk> of unit <CLKDIV> are equivalent, second instance is removed
WARNING:NgdBuild:452 - logical net 'I2C_SampClk/CLK_NUM<0>' has no driver
WARNING:NgdBuild:452 - logical net 'I2C_SampClk/CLK_NUM<1>' has no driver
WARNING:NgdBuild:452 - logical net 'I2C_SampClk/CLK_NUM<2>' has no driver
WARNING:NgdBuild:452 - logical net 'I2C_SampClk/CLK_NUM<3>' has no driver
WARNING:NgdBuild:452 - logical net 'I2C_SampClk/CLK_NUM<4>' has no driver
WARNING:NgdBuild:452 - logical net 'I2C_SampClk/CLK_NUM<5>' has no driver
WARNING:NgdBuild:452 - logical net 'I2C_SampClk/CLK_NUM<6>' has no driver
WARNING:NgdBuild:452 - logical net 'I2C_SampClk/CLK_NUM<7>' has no driver
WARNING:NgdBuild:452 - logical net 'I2C_SampClk/CLK_NUM<8>' has no driver I2C_SampClk: CLKDIV
port map (
CLK_IN=> IIC_CLKIN,
CLK_RST => IIC_RST,
CLK_CS=> IIC_CS,
CLK_NUM => IICDivNum0,
CLK_OUT => IICaaaaSampClk
);
如果就只有这个的话，这个警告又没有，现在不知道什么原因！ 自己顶下！ 现在自己清楚了警告，但是有点不明白！
signal IICDivNum0: std_logic_vector ( 8 downto 0 );
signal IICDivNum1: std_logic_vector ( 8 downto 0 );
I2C_SampClk: CLKDIV
port map (
CLK_IN=> IIC_CLKIN,
CLK_RST => IIC_RST,
CLK_CS=> IIC_CS,
CLK_NUM => IICDivNum0, --- 这里是内部的信号!
CLK_OUT => IICaaaaSampClk
）
以上是元件例化>
------------------------------------------
port (
CLK_IN : instd_logic;
CLK_RST: instd_logic;
CLK_CS : instd_logic;
CLK_NUM: instd_logic_vector ( 8 downto 0 );
CLK_OUT: out std_logic
);
------------------------------------------
这个是端口,
如果例化语句改为下面的就没有警告了.
I2C_SampClk: CLKDIV
port map (
CLK_IN=> IIC_CLKIN,
CLK_RST => IIC_RST,
CLK_CS=> IIC_CS,
CLK_NUM => IIC_NUM ( 8 downto 0 ),-- 这里改为端口
CLK_OUT => IIC_CLKOUT0
);
为什么会这样呢?希望遇到过的朋友能帮忙解释下？谢谢！ 还有，为什么只例化一个的话，可以用内部的信号呢？
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