引脚被莫明其妙地接到地上了？
Warning: Following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting resultsInfo: Pin digital_output_high has GND driving its datain port
Info: Pin digital_output_low has GND driving its datain port
此两个引脚在PIN PLANNER里是灰色的？
怎样才能解决？ ALTERA? XILINX? CPLD? FPGA?
器件型号？
软件版本？ 回楼上：
ALTERA
CPLD
EMP240
QUARTUS8.1
先谢谢。 Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
Info: Processing started: Wed Feb 25 09:44:20 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ScalerNew -c ScalerNew
Info: Found 3 design units, including 3 entities, in source file ScalerNew.v
Info: Found entity 1: ScalerNew
Info: Found entity 2: scaler_one
Info: Found entity 3: display
Info: Elaborating entity "ScalerNew" for the top level hierarchy
Info: Elaborating entity "scaler_one" for hierarchy "scaler_one:scaler0"
Info: Elaborating entity "display" for hierarchy "scaler_one:scaler0|display:display1"
Warning (10235): Verilog HDL Always Construct warning at ScalerNew.v(221): variable "temp1" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at ScalerNew.v(221): variable "temp0" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "digital_output_high0" is stuck at GND
Warning (13410): Pin "digital_output_low0" is stuck at GND
Warning (13410): Pin "digital_output_high1" is stuck at GND
Warning (13410): Pin "digital_output_low1" is stuck at GND
Info: Implemented 112 device resources after synthesis - the final resource count might be different
Info: Implemented 10 input pins
Info: Implemented 34 output pins
Info: Implemented 68 logic cells
Info: Generated suppressed messages file E:/MyAltera/ScalerNew/ScalerNew.map.smsg
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
Info: Peak virtual memory: 164 megabytes
Info: Processing ended: Wed Feb 25 09:44:22 2009
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
Info: Processing started: Wed Feb 25 09:44:23 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ScalerNew -c ScalerNew
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Selected device EPM240T100C3 for design "ScalerNew"
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM570T100C3 is compatible
Warning: No exact pin location assignment(s) for 44 pins of 44 total pins
Info: Pin clock_output0 not assigned to an exact location on the device
Info: Pin clock_output1 not assigned to an exact location on the device
Info: Pin digital_output_high0 not assigned to an exact location on the device
Info: Pin digital_output_high0 not assigned to an exact location on the device
Info: Pin digital_output_high0 not assigned to an exact location on the device
Info: Pin digital_output_high0 not assigned to an exact location on the device
Info: Pin digital_output_high0 not assigned to an exact location on the device
Info: Pin digital_output_high0 not assigned to an exact location on the device
Info: Pin digital_output_high0 not assigned to an exact location on the device
Info: Pin digital_output_high0 not assigned to an exact location on the device
Info: Pin digital_output_low0 not assigned to an exact location on the device
Info: Pin digital_output_low0 not assigned to an exact location on the device
Info: Pin digital_output_low0 not assigned to an exact location on the device
Info: Pin digital_output_low0 not assigned to an exact location on the device
Info: Pin digital_output_low0 not assigned to an exact location on the device
Info: Pin digital_output_low0 not assigned to an exact location on the device
Info: Pin digital_output_low0 not assigned to an exact location on the device
Info: Pin digital_output_low0 not assigned to an exact location on the device
Info: Pin digital_output_high1 not assigned to an exact location on the device
Info: Pin digital_output_high1 not assigned to an exact location on the device
Info: Pin digital_output_high1 not assigned to an exact location on the device
Info: Pin digital_output_high1 not assigned to an exact location on the device
Info: Pin digital_output_high1 not assigned to an exact location on the device
Info: Pin digital_output_high1 not assigned to an exact location on the device
Info: Pin digital_output_high1 not assigned to an exact location on the device
Info: Pin digital_output_high1 not assigned to an exact location on the device
Info: Pin digital_output_low1 not assigned to an exact location on the device
Info: Pin digital_output_low1 not assigned to an exact location on the device
Info: Pin digital_output_low1 not assigned to an exact location on the device
Info: Pin digital_output_low1 not assigned to an exact location on the device
Info: Pin digital_output_low1 not assigned to an exact location on the device
Info: Pin digital_output_low1 not assigned to an exact location on the device
Info: Pin digital_output_low1 not assigned to an exact location on the device
Info: Pin digital_output_low1 not assigned to an exact location on the device
Info: Pin scale_input_high not assigned to an exact location on the device
Info: Pin scale_input_high not assigned to an exact location on the device
Info: Pin scale_input_high not assigned to an exact location on the device
Info: Pin scale_input_high not assigned to an exact location on the device
Info: Pin scale_input_low not assigned to an exact location on the device
Info: Pin scale_input_low not assigned to an exact location on the device
Info: Pin scale_input_low not assigned to an exact location on the device
Info: Pin scale_input_low not assigned to an exact location on the device
Info: Pin clock_input0 not assigned to an exact location on the device
Info: Pin clock_input1 not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clock_input0" to use Global clock in PIN 14
Info: Automatically promoted signal "clock_input1" to use Global clock in PIN 12
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 42 (unused VREF, 3.3V VCCIO, 8 input, 34 output, 0 bidirectional)
Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --36 pins available
Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --42 pins available
Info: Fitter preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is pin to register delay of 12.027 ns
Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_8; Fanout = 14; PIN Node = 'scale_input_high'
Info: 2: + IC(1.771 ns) + CELL(0.125 ns) = 2.604 ns; Loc. = LAB_X7_Y3; Fanout = 3; COMB Node = 'scaler_one:scaler1|display:display1|Decoder6~12'
Info: 3: + IC(1.148 ns) + CELL(0.611 ns) = 4.363 ns; Loc. = LAB_X4_Y3; Fanout = 2; COMB Node = 'scaler_one:scaler0|display:display1|scale_number~27'
Info: 4: + IC(0.000 ns) + CELL(0.077 ns) = 4.440 ns; Loc. = LAB_X4_Y3; Fanout = 2; COMB Node = 'scaler_one:scaler0|display:display1|scale_number~21'
Info: 5: + IC(0.000 ns) + CELL(0.249 ns) = 4.689 ns; Loc. = LAB_X4_Y3; Fanout = 3; COMB Node = 'scaler_one:scaler0|display:display1|scale_number~23'
Info: 6: + IC(0.000 ns) + CELL(0.771 ns) = 5.460 ns; Loc. = LAB_X4_Y3; Fanout = 3; COMB Node = 'scaler_one:scaler0|display:display1|scale_number~18'
Info: 7: + IC(0.731 ns) + CELL(0.611 ns) = 6.802 ns; Loc. = LAB_X5_Y3; Fanout = 2; COMB Node = 'scaler_one:scaler0|Add0~132'
Info: 8: + IC(0.000 ns) + CELL(0.509 ns) = 7.311 ns; Loc. = LAB_X5_Y3; Fanout = 2; COMB Node = 'scaler_one:scaler0|Add0~137'
Info: 9: + IC(0.867 ns) + CELL(0.571 ns) = 8.749 ns; Loc. = LAB_X6_Y1; Fanout = 1; COMB Node = 'scaler_one:scaler0|Equal0~74'
Info: 10: + IC(1.314 ns) + CELL(0.125 ns) = 10.188 ns; Loc. = LAB_X5_Y3; Fanout = 9; COMB Node = 'scaler_one:scaler0|Equal0~75'
Info: 11: + IC(0.739 ns) + CELL(1.100 ns) = 12.027 ns; Loc. = LAB_X6_Y3; Fanout = 2; REG Node = 'scaler_one:scaler0|temp_counter'
Info: Total cell delay = 5.457 ns ( 45.37 % )
Info: Total interconnect delay = 6.570 ns ( 54.63 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 6% of the available device resources
Info: Peak interconnect usage is 6% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Warning: Following 4 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin digital_output_high0 has GND driving its datain port
Info: Pin digital_output_low0 has GND driving its datain port
Info: Pin digital_output_high1 has GND driving its datain port
Info: Pin digital_output_low1 has GND driving its datain port
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file E:/MyAltera/ScalerNew/ScalerNew.fit.smsg
Info: Parallel compilation was enabled and used an average of 1.0 processors and a maximum of 2 processors out of 2 processors allowed
Info: Less than 1% of process time was spent using more than one processor
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 183 megabytes
Info: Processing ended: Wed Feb 25 09:44:25 2009
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
Info: Processing started: Wed Feb 25 09:44:26 2009
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ScalerNew -c ScalerNew
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 140 megabytes
Info: Processing ended: Wed Feb 25 09:44:27 2009
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
Info: Processing started: Wed Feb 25 09:44:28 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ScalerNew -c ScalerNew
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clock_input0" is an undefined clock
Info: Assuming node "clock_input1" is an undefined clock
Info: Clock "clock_input0" has Internal fmax of 189.93 MHz between source register "scaler_one:scaler0|temp_counter" and destination register "scaler_one:scaler0|clock_output" (period= 5.265 ns)
Info: + Longest register to register delay is 4.822 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y3_N2; Fanout = 4; REG Node = 'scaler_one:scaler0|temp_counter'
Info: 2: + IC(1.273 ns) + CELL(0.319 ns) = 1.592 ns; Loc. = LC_X6_Y1_N7; Fanout = 1; COMB Node = 'scaler_one:scaler0|Equal0~74'
Info: 3: + IC(1.163 ns) + CELL(0.125 ns) = 2.880 ns; Loc. = LC_X5_Y3_N9; Fanout = 9; COMB Node = 'scaler_one:scaler0|Equal0~75'
Info: 4: + IC(1.573 ns) + CELL(0.369 ns) = 4.822 ns; Loc. = LC_X5_Y1_N2; Fanout = 2; REG Node = 'scaler_one:scaler0|clock_output'
Info: Total cell delay = 0.813 ns ( 16.86 % )
Info: Total interconnect delay = 4.009 ns ( 83.14 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clock_input0" to destination register is 2.093 ns
Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 9; CLK Node = 'clock_input0'
Info: 2: + IC(0.792 ns) + CELL(0.574 ns) = 2.093 ns; Loc. = LC_X5_Y1_N2; Fanout = 2; REG Node = 'scaler_one:scaler0|clock_output'
Info: Total cell delay = 1.301 ns ( 62.16 % )
Info: Total interconnect delay = 0.792 ns ( 37.84 % )
Info: - Longest clock path from clock "clock_input0" to source register is 2.093 ns
Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 9; CLK Node = 'clock_input0'
Info: 2: + IC(0.792 ns) + CELL(0.574 ns) = 2.093 ns; Loc. = LC_X6_Y3_N2; Fanout = 4; REG Node = 'scaler_one:scaler0|temp_counter'
Info: Total cell delay = 1.301 ns ( 62.16 % )
Info: Total interconnect delay = 0.792 ns ( 37.84 % )
Info: + Micro clock to output delay of source is 0.235 ns
Info: + Micro setup delay of destination is 0.208 ns
Info: Clock "clock_input1" has Internal fmax of 223.16 MHz between source register "scaler_one:scaler1|temp_counter" and destination register "scaler_one:scaler1|temp_counter" (period= 4.481 ns)
Info: + Longest register to register delay is 4.038 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y1_N1; Fanout = 4; REG Node = 'scaler_one:scaler1|temp_counter'
Info: 2: + IC(0.800 ns) + CELL(0.571 ns) = 1.371 ns; Loc. = LC_X6_Y1_N0; Fanout = 1; COMB Node = 'scaler_one:scaler1|Equal0~71'
Info: 3: + IC(0.445 ns) + CELL(0.462 ns) = 2.278 ns; Loc. = LC_X6_Y1_N9; Fanout = 9; COMB Node = 'scaler_one:scaler1|Equal0~75'
Info: 4: + IC(0.660 ns) + CELL(1.100 ns) = 4.038 ns; Loc. = LC_X7_Y1_N7; Fanout = 2; REG Node = 'scaler_one:scaler1|temp_counter'
Info: Total cell delay = 2.133 ns ( 52.82 % )
Info: Total interconnect delay = 1.905 ns ( 47.18 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clock_input1" to destination register is 2.093 ns
Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_12; Fanout = 9; CLK Node = 'clock_input1'
Info: 2: + IC(0.792 ns) + CELL(0.574 ns) = 2.093 ns; Loc. = LC_X7_Y1_N7; Fanout = 2; REG Node = 'scaler_one:scaler1|temp_counter'
Info: Total cell delay = 1.301 ns ( 62.16 % )
Info: Total interconnect delay = 0.792 ns ( 37.84 % )
Info: - Longest clock path from clock "clock_input1" to source register is 2.093 ns
Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_12; Fanout = 9; CLK Node = 'clock_input1'
Info: 2: + IC(0.792 ns) + CELL(0.574 ns) = 2.093 ns; Loc. = LC_X7_Y1_N1; Fanout = 4; REG Node = 'scaler_one:scaler1|temp_counter'
Info: Total cell delay = 1.301 ns ( 62.16 % )
Info: Total interconnect delay = 0.792 ns ( 37.84 % )
Info: + Micro clock to output delay of source is 0.235 ns
Info: + Micro setup delay of destination is 0.208 ns
Info: tsu for register "scaler_one:scaler0|clock_output" (data pin = "scale_input_high", clock pin = "clock_input0") is 10.267 ns
Info: + Longest pin to register delay is 12.152 ns
Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_8; Fanout = 14; PIN Node = 'scale_input_high'
Info: 2: + IC(1.717 ns) + CELL(0.571 ns) = 2.996 ns; Loc. = LC_X4_Y1_N3; Fanout = 2; COMB Node = 'scaler_one:scaler0|display:display1|Add0~207'
Info: 3: + IC(1.230 ns) + CELL(0.596 ns) = 4.822 ns; Loc. = LC_X4_Y3_N4; Fanout = 3; COMB Node = 'scaler_one:scaler0|display:display1|scale_number~23'
Info: 4: + IC(0.000 ns) + CELL(0.609 ns) = 5.431 ns; Loc. = LC_X4_Y3_N5; Fanout = 3; COMB Node = 'scaler_one:scaler0|display:display1|scale_number~18'
Info: 5: + IC(0.692 ns) + CELL(0.611 ns) = 6.734 ns; Loc. = LC_X5_Y3_N5; Fanout = 2; COMB Node = 'scaler_one:scaler0|Add0~132'
Info: 6: + IC(0.000 ns) + CELL(0.509 ns) = 7.243 ns; Loc. = LC_X5_Y3_N6; Fanout = 2; COMB Node = 'scaler_one:scaler0|Add0~137'
Info: 7: + IC(1.217 ns) + CELL(0.462 ns) = 8.922 ns; Loc. = LC_X6_Y1_N7; Fanout = 1; COMB Node = 'scaler_one:scaler0|Equal0~74'
Info: 8: + IC(1.163 ns) + CELL(0.125 ns) = 10.210 ns; Loc. = LC_X5_Y3_N9; Fanout = 9; COMB Node = 'scaler_one:scaler0|Equal0~75'
Info: 9: + IC(1.573 ns) + CELL(0.369 ns) = 12.152 ns; Loc. = LC_X5_Y1_N2; Fanout = 2; REG Node = 'scaler_one:scaler0|clock_output'
Info: Total cell delay = 4.560 ns ( 37.52 % )
Info: Total interconnect delay = 7.592 ns ( 62.48 % )
Info: + Micro setup delay of destination is 0.208 ns
Info: - Shortest clock path from clock "clock_input0" to destination register is 2.093 ns
Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 9; CLK Node = 'clock_input0'
Info: 2: + IC(0.792 ns) + CELL(0.574 ns) = 2.093 ns; Loc. = LC_X5_Y1_N2; Fanout = 2; REG Node = 'scaler_one:scaler0|clock_output'
Info: Total cell delay = 1.301 ns ( 62.16 % )
Info: Total interconnect delay = 0.792 ns ( 37.84 % )
Info: tco from clock "clock_input0" to destination pin "clock_output0" through register "scaler_one:scaler0|clock_output" is 5.028 ns
Info: + Longest clock path from clock "clock_input0" to source register is 2.093 ns
Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 9; CLK Node = 'clock_input0'
Info: 2: + IC(0.792 ns) + CELL(0.574 ns) = 2.093 ns; Loc. = LC_X5_Y1_N2; Fanout = 2; REG Node = 'scaler_one:scaler0|clock_output'
Info: Total cell delay = 1.301 ns ( 62.16 % )
Info: Total interconnect delay = 0.792 ns ( 37.84 % )
Info: + Micro clock to output delay of source is 0.235 ns
Info: + Longest register to pin delay is 2.700 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y1_N2; Fanout = 2; REG Node = 'scaler_one:scaler0|clock_output'
Info: 2: + IC(1.246 ns) + CELL(1.454 ns) = 2.700 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'clock_output0'
Info: Total cell delay = 1.454 ns ( 53.85 % )
Info: Total interconnect delay = 1.246 ns ( 46.15 % )
Info: Longest tpd from source pin "scale_input_high" to destination pin "digital_output_high1" is 5.892 ns
Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_8; Fanout = 14; PIN Node = 'scale_input_high'
Info: 2: + IC(1.760 ns) + CELL(0.319 ns) = 2.787 ns; Loc. = LC_X4_Y1_N2; Fanout = 2; COMB Node = 'scaler_one:scaler0|display:display1|WideOr9~13'
Info: 3: + IC(1.651 ns) + CELL(1.454 ns) = 5.892 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 'digital_output_high1'
Info: Total cell delay = 2.481 ns ( 42.11 % )
Info: Total interconnect delay = 3.411 ns ( 57.89 % )
Info: th for register "scaler_one:scaler1|clock_output" (data pin = "scale_input_low", clock pin = "clock_input1") is -4.592 ns
Info: + Longest clock path from clock "clock_input1" to destination register is 2.093 ns
Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_12; Fanout = 9; CLK Node = 'clock_input1'
Info: 2: + IC(0.792 ns) + CELL(0.574 ns) = 2.093 ns; Loc. = LC_X6_Y1_N6; Fanout = 2; REG Node = 'scaler_one:scaler1|clock_output'
Info: Total cell delay = 1.301 ns ( 62.16 % )
Info: Total interconnect delay = 0.792 ns ( 37.84 % )
Info: + Micro hold delay of destination is 0.138 ns
Info: - Shortest pin to register delay is 6.823 ns
Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_58; Fanout = 8; PIN Node = 'scale_input_low'
Info: 2: + IC(1.209 ns) + CELL(0.462 ns) = 2.379 ns; Loc. = LC_X4_Y2_N6; Fanout = 3; COMB Node = 'scaler_one:scaler0|display:display1|WideOr0~17'
Info: 3: + IC(1.168 ns) + CELL(0.571 ns) = 4.118 ns; Loc. = LC_X5_Y3_N0; Fanout = 2; COMB Node = 'scaler_one:scaler0|Add0~129'
Info: 4: + IC(1.114 ns) + CELL(0.462 ns) = 5.694 ns; Loc. = LC_X6_Y1_N8; Fanout = 1; COMB Node = 'scaler_one:scaler1|Equal0~72'
Info: 5: + IC(0.191 ns) + CELL(0.125 ns) = 6.010 ns; Loc. = LC_X6_Y1_N9; Fanout = 9; COMB Node = 'scaler_one:scaler1|Equal0~75'
Info: 6: + IC(0.444 ns) + CELL(0.369 ns) = 6.823 ns; Loc. = LC_X6_Y1_N6; Fanout = 2; REG Node = 'scaler_one:scaler1|clock_output'
Info: Total cell delay = 2.697 ns ( 39.53 % )
Info: Total interconnect delay = 4.126 ns ( 60.47 % )
Info: Parallel compilation was enabled but no parallel operations were performed
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 127 megabytes
Info: Processing ended: Wed Feb 25 09:44:30 2009
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01
Info: Quartus II Full Compilation was successful. 0 errors, 11 warnings module ScalerNew(clock_input0,clock_input1,scale_input_high,scale_input_low,
clock_output0,clock_output1,digital_output_high0,digital_output_low0,
digital_output_high1,digital_output_low1);
parameter width4=4,width8=8;
input clock_input0,clock_input1;
input scale_input_high,scale_input_low;
output clock_output0,clock_output1;
output digital_output_high0,digital_output_low0,
digital_output_high1,digital_output_low1;
reg temp_counter;
wire clock_output0,clock_output1;
wire scale_input_high,scale_input_low;
wire scale_number;
wire digital_output_high0,digital_output_low0,
digital_output_high1,digital_output_low1;
wire clock_input0,clock_input1;
scaler_one scaler0(clock_input0,scale_input_high,scale_input_low,
clock_output0,digital_output_high0,digital_output_low0);
scaler_one scaler1(clock_input1,scale_input_high,scale_input_low,
clock_output1,digital_output_high1,digital_output_low1);
endmodule
module scaler_one(clock_input,scale_input_high,scale_input_low,
clock_output,digital_output_high,digital_output_low);
parameter width4=4,width8=8;
input clock_input;
input scale_input_high,scale_input_low;
output clock_output;
output digital_output_high,digital_output_low;
reg clock_output;
reg temp_counter;
wire scale_input_high,scale_input_low;
wire scale_number;
wire digital_output_high,digital_output_low;
wire clock_input;
display display1(scale_input_high,scale_input_low,scale_number,
digital_output_high,digital_output_low);
always@(posedge clock_input)
begin
if(temp_counter==scale_number-8'h1)
begin
clock_output=~clock_output;
temp_counter<=8'h0;
end
else
temp_counter<=temp_counter+8'h1;
end
endmodule
module display(scale_input_high,scale_input_low,scale_number,digital_output_high,digital_output_low);
parameter
width4=4,
width8=8;
input scale_input_high,scale_input_low;
output scale_number;
output digital_output_high,digital_output_low;
reg scale_number;
reg digital_output_high,digital_output_low;
reg temp0,temp1;
always@(scale_input_high or scale_input_low)
begin
case(scale_input_low)
4'b0000:
begin
temp0<=0;
digital_output_low<=63;
end
4'b0001:
begin
temp0<=1;
digital_output_low<=6;
end
4'b0010:
begin
temp0<=2;
digital_output_low<=91;
end
4'b0011:
begin
temp0<=3;
digital_output_low<=79;
end
4'b0100:
begin
temp0<=4;
digital_output_low<=102;
end
4'b0101:
begin
temp0<=5;
digital_output_low<=109;
end
4'b0110:
begin
temp0<=6;
digital_output_low<=125;
end
4'b0111:
begin
temp0<=7;
digital_output_low<=7;
end
4'b1000:
begin
temp0<=8;
digital_output_low<=127;
end
4'b1001:
begin
temp0<=9;
digital_output_low<=111;
end
default:
begin
temp0<=0;
digital_output_low<=63;
end
endcase
case(scale_input_high)
4'b0000:
begin
temp1<=0;
digital_output_high<=63;
end
4'b0001:
begin
temp1<=1;
digital_output_high<=6;
end
4'b0010:
begin
temp1<=2;
digital_output_high<=91;
end
4'b0011:
begin
temp1<=3;
digital_output_high<=79;
end
4'b0100:
begin
temp1<=4;
digital_output_high<=102;
end
4'b0101:
begin
temp1<=5;
digital_output_high<=109;
end
4'b0110:
begin
temp1<=6;
digital_output_high<=125;
end
4'b0111:
begin
temp1<=7;
digital_output_high<=7;
end
4'b1000:
begin
temp1<=8;
digital_output_high<=127;
end
4'b1001:
begin
temp1<=9;
digital_output_high<=111;
end
default:
begin
temp1<=0;
digital_output_high<=63;
end
endcase
scale_number<=temp1*8'd10+temp0;
end
endmodule 3楼是警告信息。4楼是源代码。
实现的东西是很简单的，根据scale_input_high（4位BCD码）和scale_input_low（4位BCD码）来决定分频系数，然后对clock_input进行分频。
谁能帮忙解释一下有些引脚被接地的原因？ 哪位兄台能帮忙解释一下？先谢谢了。 Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "digital_output_high0" is stuck at GND
Warning (13410): Pin "digital_output_low0" is stuck at GND
Warning (13410): Pin "digital_output_high1" is stuck at GND
Warning (13410): Pin "digital_output_low1" is stuck at GND
真的有点不明白，总共是八位的数据，为什么单单第八位被“骗接到地”呢？ 估计是那些引脚你没有用到 哈哈，ilan2003 小松工程，你真厉害，真的是如此。
那个输出是数码管的，小数点我没有用。
非常谢谢！ arh感谢了！
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