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楼主 |
发表于 2009-2-25 09:46:52
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module ScalerNew(clock_input0,clock_input1,scale_input_high,scale_input_low,
clock_output0,clock_output1,digital_output_high0,digital_output_low0,
digital_output_high1,digital_output_low1);
parameter width4=4,width8=8;
input clock_input0,clock_input1;
input[width4-1:0] scale_input_high,scale_input_low;
output clock_output0,clock_output1;
output[width8-1:0] digital_output_high0,digital_output_low0,
digital_output_high1,digital_output_low1;
reg[width8-1:0] temp_counter;
wire clock_output0,clock_output1;
wire[width4-1:0] scale_input_high,scale_input_low;
wire[width8-1:0] scale_number;
wire[width8-1:0] digital_output_high0,digital_output_low0,
digital_output_high1,digital_output_low1;
wire clock_input0,clock_input1;
scaler_one scaler0(clock_input0,scale_input_high,scale_input_low,
clock_output0,digital_output_high0,digital_output_low0);
scaler_one scaler1(clock_input1,scale_input_high,scale_input_low,
clock_output1,digital_output_high1,digital_output_low1);
endmodule
module scaler_one(clock_input,scale_input_high,scale_input_low,
clock_output,digital_output_high,digital_output_low);
parameter width4=4,width8=8;
input clock_input;
input[width4-1:0] scale_input_high,scale_input_low;
output clock_output;
output[width8-1:0] digital_output_high,digital_output_low;
reg clock_output;
reg[width8-1:0] temp_counter;
wire[width4-1:0] scale_input_high,scale_input_low;
wire[width8-1:0] scale_number;
wire[width8-1:0] digital_output_high,digital_output_low;
wire clock_input;
display display1(scale_input_high,scale_input_low,scale_number,
digital_output_high,digital_output_low);
always@(posedge clock_input)
begin
if(temp_counter==scale_number-8'h1)
begin
clock_output=~clock_output;
temp_counter<=8'h0;
end
else
temp_counter<=temp_counter+8'h1;
end
endmodule
module display(scale_input_high,scale_input_low,scale_number,digital_output_high,digital_output_low);
parameter
width4=4,
width8=8;
input[width4-1:0] scale_input_high,scale_input_low;
output[width8-1:0] scale_number;
output[width8-1:0] digital_output_high,digital_output_low;
reg[width8-1:0] scale_number;
reg[width8-1:0] digital_output_high,digital_output_low;
reg[width8-1:0] temp0,temp1;
always@(scale_input_high or scale_input_low)
begin
case(scale_input_low)
4'b0000:
begin
temp0<=0;
digital_output_low<=63;
end
4'b0001:
begin
temp0<=1;
digital_output_low<=6;
end
4'b0010:
begin
temp0<=2;
digital_output_low<=91;
end
4'b0011:
begin
temp0<=3;
digital_output_low<=79;
end
4'b0100:
begin
temp0<=4;
digital_output_low<=102;
end
4'b0101:
begin
temp0<=5;
digital_output_low<=109;
end
4'b0110:
begin
temp0<=6;
digital_output_low<=125;
end
4'b0111:
begin
temp0<=7;
digital_output_low<=7;
end
4'b1000:
begin
temp0<=8;
digital_output_low<=127;
end
4'b1001:
begin
temp0<=9;
digital_output_low<=111;
end
default:
begin
temp0<=0;
digital_output_low<=63;
end
endcase
case(scale_input_high)
4'b0000:
begin
temp1<=0;
digital_output_high<=63;
end
4'b0001:
begin
temp1<=1;
digital_output_high<=6;
end
4'b0010:
begin
temp1<=2;
digital_output_high<=91;
end
4'b0011:
begin
temp1<=3;
digital_output_high<=79;
end
4'b0100:
begin
temp1<=4;
digital_output_high<=102;
end
4'b0101:
begin
temp1<=5;
digital_output_high<=109;
end
4'b0110:
begin
temp1<=6;
digital_output_high<=125;
end
4'b0111:
begin
temp1<=7;
digital_output_high<=7;
end
4'b1000:
begin
temp1<=8;
digital_output_high<=127;
end
4'b1001:
begin
temp1<=9;
digital_output_high<=111;
end
default:
begin
temp1<=0;
digital_output_high<=63;
end
endcase
scale_number<=temp1*8'd10+temp0;
end
endmodule |
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