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发表于 2008-4-26 15:39:42
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UC3A 数据手册特性翻译
版主技术火腿个人急速翻译,错误不保证请大家参照原文,请各位大虾指正错误,谢谢啦
UC3A
1、高性能,低功耗,AVR32 32位微控制器
-支持精简单周期RISC指令集以及DSP指令集
-支持读,修改,写入指令以及基本位操作
-达到1.38DMIPS/MHZ
在66MHz(1周期等待)FLASH运行的条件下达到83DMIPS处理能力
在33MHz(0周期等待)FLASH运行的条件下达到45DMIPS处理能力
-支持MPU单元
2、多层总线系统
-通过在各级总线上的高速度数据交换用以增加性能
-15个独立的外设DMA通道用以增加外设的数据交换速度
3、内部集成高速FLASH
-支持512K Bytes,256K Bytes,128K Bytes版本
-最高单周期访问速度达到33MHz
-在最高速时通过预取缓存优化指令执行
-4ms页编程时间,8ms全擦除时间
-10万次写入次数,数据可以保存15年
-FLASH可分别设置保密位以及用户自定义的数据区域
4、内部集成高速SRAM,全速单周期访问能力
-64K Bytes(512KB和256KB 版本),32K Bytes(128KB 版本)
5、外部扩展存储器接口(仅AT32UC3A0系列支持)
-支持兼容SDRAM/SRAM存储器总线(16位数据及24位地址总线)
6、中断控制器
-硬件自动处理中断,支持低延迟快速中断服务。用户可自行编程优先级
7、系统功能
-电源及时钟管理模块内部集成了RC时钟以及32KHz晶体振荡器
-支持两个多用途的晶体振荡器及两个PLL锁相环模块。通过组合可设定独立的CPU及外设的工作频率。
-支持看门狗定时器,实时时钟定时器
8、USB
-支持全速Device 2.0协议以及On-The-Go(OTG)全速及低速协议
-可灵活设置终点及控制专用的DMA通道
-内部集成了带上拉的收发器
9、支持10M/100M以太网介质访问控制子层协议接口(MAC)
-内部集成802.3介质网络控制子层协议控制器
-支持介质无关接口(MII)以及精简版的MII接口(RMII)
10、内部集成3个16位定时计数器
-支持三个额外的时钟输入,支持PWM,输入捕捉以及各种计数功能
11、支持一组7个通道16位PWM功能
12、支持4组USART
-内部集成独立的波特率发生器,支持SPI,IrDA和ISO7816接口
-支持硬件流控制,RS485接口和Modem接口
13、支持两组拥有主从功能的SPI接口,并设有片选功能
14、支持一个同步串行协议控制器(SSC)
-支持I2S协议和通用基础帧协议
15、支持一个兼容I2C,速度高达400kbit/s的TWI接口
16、支持一组8个通道的模数转换器
17、支持16位立体声数据流
-采样频率最高达50KHz
18、片上仿真系统(JTAG 接口)
-支持 Nexus Class 2+协议,芯片运行控制,无打断读取数据以及程序跟踪
19、100脚 TQFP封装(69 GPIO)144脚 LQFP封装(109 GPIO)
20IO提供5V的输入承受能力
21、支持单3.3V工作电压,以双1.8~3.3V工作电压
英文原文:
UC3A
Features
• High Performance, Low Power AVR®32 UC 32-Bit Microcontroller
– Compact Single-cycle RISC Instruction Set Including DSP Instruction Set
– Read-Modify-Write Instructions and Atomic Bit Manipulation
– Performing 1.38 DMIPS / MHz
Up to 83 DMIPS Running at 66 MHz from Flash (1 Wait-State)
Up to 45 DMIPS Running at 33MHz from Flash (0 Wait-State)
– Memory Protection Unit
• Multi-hierarchy Bus System
– High-Performance Data Transfers on Separate Buses for Increased Performance
– 15 Peripheral DMA Channels Improves Speed for Peripheral Communication
• Internal High-Speed Flash
– 512K Bytes, 256K Bytes, 128K Bytes Versions
– Single Cycle Access up to 33 MHz
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
– 4ms Page Programming Time and 8ms Full-Chip Erase Time
– 100,000 Write Cycles, 15-year Data Retention Capability
– Flash Security Locks and User Defined Configuration Area
• Internal High-Speed SRAM, Single-Cycle Access at Full Speed
– 64K Bytes (512KB and 256KB Flash), 32K Bytes (128KB Flash)
• External Memory Interface on AT32UC3A0 Derivatives
– SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses)
• Interrupt Controller
– Autovectored Low Latency Interrupt Service with Programmable Priority
• System Functions
– Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator
– Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL) allowing
Independant CPU Frequency from USB Frequency
– Watchdog Timer, Real-Time Clock Timer
• Universal Serial Bus (USB)
– Device 2.0 Full Speed and On-The-Go (OTG) Low Speed and Full Speed
– Flexible End-Point Configuration and Management with Dedicated DMA Channels
– On-chip Transceivers Including Pull-Ups
• Ethernet MAC 10/100 Mbps interface
– 802.3 Ethernet Media Access Controller
– Supports Media Independent Interface (MII) and Reduced MII (RMII)
• One Three-Channel 16-bit Timer/Counter (TC)
– Three External Clock Inputs, PWM, Capture and Various Counting Capabilities
• One 7-Channel 16-bit Pulse Width Modulation Controller (PWM)
• Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– Independant Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces
– Support for Hardware Handshaking, RS485 Interfaces and Modem Line
• Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals
• One Synchronous Serial Protocol Controller
– Supports I2S and Generic Frame-Based Protocols
• One Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible
• One 8-channel 10-bit Analog-To-Digital Converter
• 16-bit Stereo Audio Bitstream
– Sample Rate Up to 50 KHz
• On-Chip Debug System (JTAG interface)
– Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace
• 100-pin TQFP (69 GPIO pins), 144-pin LQFP (109 GPIO pins)
• 5V Input Tolerant I/Os
• Single 3.3V Power Supply or Dual 1.8V-3.3V Power Supply |
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