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楼主 |
发表于 2021-2-27 22:36:36
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贴一下代码,发送端:
CE_L;//CE=0; // chip enable
CS_H;//CSN=1; // Spi disable
SCK_L;//SCK=0; //
SPI_RW_Reg(WRITE_REG_24L01 + STATUS, 0xff); // clear irq flag
SPI_RW(FLUSH_TX); //clear tx fifo
SPI_RW(FLUSH_RX); //clear rx fifo
SPI_Write_Buf(WRITE_REG_24L01 + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH); // Writes TX_Address to nRF24L01
SPI_Write_Buf(WRITE_REG_24L01 + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); // RX_Addr0 same as TX_Adr for Auto.Ack
SPI_Write_Buf(WR_TX_PLOAD, TxBuf, TX_PLOAD_WIDTH); // Writes data to TX payload
SPI_RW_Reg(WRITE_REG_24L01 + EN_AA, 0x01); // Enable Auto.Ack:Pipe0
SPI_RW_Reg(WRITE_REG_24L01 + EN_RXADDR, 0x01); // Enable Pipe0
SPI_RW_Reg(WRITE_REG_24L01 + SETUP_RETR, 0x12); // 500us , 10 retrans...
SPI_RW_Reg(WRITE_REG_24L01 + RF_CH, ch_freq); // Select RF channel 40
SPI_RW_Reg(WRITE_REG_24L01 + RF_SETUP, 0x07); // TX_PWR:0dBm, Datarate:2Mbps, LNA:HCURR
SPI_RW_Reg(WRITE_REG_24L01 + CONFIG, 0x0e); // Set PWR_UP bit, enable CRC(2 bytes) & Prim:TX. MAX_RT & TX_DS enabled..
CE_H;
while(IRQ_D == 1); //µÈ´ý·¢ËÍÍê±Ï
接收端:
if(first_flag == 0)
{//只初始化时运行1次
first_flag = 1;
CE_L;//CE=0; // chip enable
CS_H;//CSN=1; // Spi disable
SCK_L;//SCK=0; //
SPI_RW_Reg(WRITE_REG_24L01 + STATUS, 0xff); // clear irq flag
SPI_RW(FLUSH_TX); //clear tx fifo
SPI_RW(FLUSH_RX); //clear rx fifo
SPI_Write_Buf(WRITE_REG_24L01 + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH); // Writes TX_Address to nRF24L01
SPI_Write_Buf(WRITE_REG_24L01 + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); // Use the same address on the RX device as the TX device
SPI_RW_Reg(WRITE_REG_24L01 + EN_AA, 0x01); // 1 Enable Auto.Ack:Pipe0
SPI_RW_Reg(WRITE_REG_24L01 + EN_RXADDR, 0x01); // Enable Pipe0
SPI_RW_Reg(WRITE_REG_24L01 + RF_CH, freq); // Select RF channel 40
SPI_RW_Reg(WRITE_REG_24L01 + RX_PW_P0, TX_PLOAD_WIDTH); // Select same RX payload width as TX Payload width
SPI_RW_Reg(WRITE_REG_24L01 + RF_SETUP, 0x07); // TX_PWR:0dBm, Datarate:2Mbps, LNA:HCURR
SPI_RW_Reg(WRITE_REG_24L01 + CONFIG, 0x0f); // Set PWR_UP bit, enable CRC(2 bytes) & Prim:RX. RX_DR enabled..
CE_H;
HAL_Delay(2);
}
if(IRQ_D == 0)
{
i = SPI_Read(STATUS);
if(i&(1<<6)) // STATUS's bit6 is rx flag
{
SPI_Read_Buf(RD_RX_PLOAD,RxBuf,TX_PLOAD_WIDTH);// read receive payload from RX_FIFO buffer
SPI_RW_Reg(WRITE_REG_24L01 + STATUS, 0xff); // clear irq flag
SPI_RW(FLUSH_TX); //clear tx fifo
SPI_RW(FLUSH_RX); //clear rx fifo
send_uart_byte_array(1, RxBuf, 32);
}
} |
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