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发表于 2021-2-7 16:14:51
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本帖最后由 javabean 于 2021-2-7 16:20 编辑
The quiescent state on the bus is a logical "1" (Mark), i.e. the bus voltage is 36 V at the
repeater, and the slaves require a maximum constant quiescent current of 1.5 mA each.
The repeater must adjust itself to the quiescent current level (Mark), and interpret an increase of
the bus current of 11-20 mA as representing a space. This can be realized with acceptable
complexity only when the mark state is defined as 36 V. This means that at any instant,
transmission is possible in only one direction - either from master to slave, or slave to master
(Half Duplex).
Powering of the Processor
The TSS721 provides a nominal voltage of 3.3 V at its VDD Pin, in order to supply power
to a microprocessor. When limited to a standard load, according to the data sheet this
processor may however consume an average current of about 600 µA. For pulse current
requirements, use is made of the reservoir capacitor STC. When connection is made to the
bus, this capacitor will be charged at up to 7 V, and the power supply at the VDD pin is
activated at VSTC = 6 V.
好像是用电容储存电力的，官方手册说法和你客户说法一致，有参考电路：
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