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发表于 2018-4-27 07:48:18
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# Copyright (c) 2015, XMOS Ltd, All rights reserved
# Disclaimer:
# XMOS uses the SABRE9018Q2C DAC chip, an ESS Technology device.
# "ESS Technology", "ESS Technology, Inc" "SABRE" and "ESS" are
# trademarks or service marks of ESS. ESS' trademarks may not be
# used in connection with any product or service that is not ESS',
# in any manner that is likely to cause confusion among customers,
# or in any manner that disparages or discredits ESS. ESS reserves
# all intellectual property rights concerning hardware design and
# software included in the SABRE9018Q2C DAC. Copying, distribution
# and any other use of hardware design and software is prohibited
# without written permission of ESS, except and only to the extent
# otherwise provided in regulations of mandatory law.
####################################################################
# xCORE-AUDIO Hi-Res 2 DAC/HPA reference platform configuration file
####################################################################
# USB Identification
VENDOR_ID = 0x20B1 //这个和下一个PID可以修改成fiio或者其他厂家的
PRODUCT_ID = 0x3066
# Format of the given USB strings
# ASCII = 0
# UNICODE = 1
# If format is mentioned as 1 (UNICODE), then the following
# USB strings are interpreted as unicode instead of ascii.
STRING_FORMAT = 0
VENDOR_STRING = "XMOS"
PRODUCT_STRING = "xCORE-AUDIO Hi-Res 2"
SERIAL_STRING = ''
LANGUAGE_ID = 0x0409
# Power options
MAX_POWER = 0xFA
SELF_POWER_ENABLE = 0
# USB Audio class 1.0 enable/disable
UAC_1_ENABLE = 0
# USB HID inputs enable/disable
HID_INPUTS_ENABLE = 0
# I2S data formats
# I2S_DEFAULT = 0
# I2S_LEFT_ALIGNED = 1
# I2S_RIGHT_ALIGNED = 2
#
I2S_DATA_FORMAT = 0
# Audio sample rates enable/disable
# Bitmap to enable/disable each supported sample rate.
# | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 |
# | 352.8K | 176.4K | 88.2K | 44.1K | 384K | 192K | 96K | 48K |
SAMPLE_RATE_BITMAP = 0b11111111
# Any variables required for writing event actions can be declared here
# Example: I2C address of the DAC can be set as a variable called
# DAC_I2C_ADDR = 0x48; For ease of writing I2C_WRITE command, the register
# addresses can also be set to variables.
# DAC I2C address
SABRE9018Q2C_I2C_ADDR = 0x48
# PLL I2C address
SI5351A_I2C_ADDR = 0x62
# DAC register addresses
SABRE9018Q2C_INPUT_CONFIG = 0x01 # Register 1 - Input Config
SABRE9018Q2C_GEN_SETTING = 0x07 # Register 7 - General Settings
SABRE9018Q2C_MASTER_MODE = 0x0A # Register 10 - Master Mode Control
SABRE9018Q2C_SOFT_START = 0x0E # Register 14 - Soft Start Settings
SABRE9018Q2C_VOLUME1 = 0x0F # Register 15 - Volume 1
SABRE9018Q2C_VOLUME2 = 0x10 # Register 16 - Volume 2
SABRE9018Q2C_CHIP_STATUS = 0x40 # Register 64 - Chip Status
SABRE9018Q2C_HP_AMP_CTRL = 0x2A # Register 42 - Headphone Amp Control
# PLL register addresses
SI5351A_OE_CTRL = 0x03 # Register 3 - Output Enable Control
SI5351A_FANOUT_EN = 0xBB # Register 187 - Fanout Enable Control
SI5351A_MS0_R0_DIV = 0x2C # Register 44 - Multisynth0 Parameters - R0_DIV[2:0], MS0_DIVBY4[1:0] and MS0_P1[17:16];
SI5351A_MS2_R2_DIV = 0x3C # Register 60 - Multisynth2 Parameters - R2_DIV[2:0], MS2_DIVBY4[1:0] and MS2_P1[17:16];
SI5351A_CLK0_CTRL = 0x10 # Register 16 - CLK0 Control
SI5351A_MS0_P1_UPPER = 0x2D # Register 45 - Multisynth0 Parameters - MS0_P1[15:8]
SI5351A_MS0_P2_LOWER = 0x31 # Register 49 - Multisynth0 Parameters - MS0_P2[7:0]
SI5351A_CLK2_CTRL = 0x12 # Register 18 - CLK2 Control
SI5351A_MS2_P1_UPPER = 0x3D # Register 61 - Multisynth2 Parameters - MS2_P1[15:8]
SI5351A_MS2_P2_LOWER = 0x41 # Register 65 - Multisynth2 Parameters - MS2_P2[7:0]
#GPIO variables
GPIO_DAC_RST_N = 3 # GPIO_3 is connected to DAC's reset line
GPIO_LED_A = 0 # GPIO_0 is connected to LED A
GPIO_LED_B = 1 # GPIO_1 is connected to LED B
# Events and their actions
# System initialize event
EVT_SYS_INIT = [
GPIO(GPIO_DAC_RST_N, LOW), #// DAC in reset
I2C_WRITE(SI5351A_I2C_ADDR, SI5351A_OE_CTRL, 0xFD), # Disable CLK0 (MCLK_IN) and CLK2 (MCLK_DAC)
I2C_WRITE(SI5351A_I2C_ADDR, SI5351A_FANOUT_EN, 0xD0), # Enable Fanout of MS0
I2C_WRITE(SI5351A_I2C_ADDR, SI5351A_CLK2_CTRL, 0X69), # Setup CLK2 ouput
I2C_WRITE(SI5351A_I2C_ADDR, SI5351A_MS0_R0_DIV, 0X10), # Change R0 divider 2
I2C_WRITE(SI5351A_I2C_ADDR, SI5351A_MS2_R2_DIV, 0X30), # Change R2 divider 8
I2C_WRITE(SI5351A_I2C_ADDR, SI5351A_MS0_P2_LOWER, 0X00), # Write lower bits of P2
DELAY_MS(1), # 1ms delay for MultiSynth output to settle
I2C_WRITE(SI5351A_I2C_ADDR, SI5351A_OE_CTRL, 0XF8), # Enable all the clock outputs
GPIO(GPIO_DAC_RST_N, HIGH), # DAC out of reset
DELAY_MS(1), # 1ms delay for DAC
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x0A), # Set soft_start to 0: Ramp the output to ground
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_HP_AMP_CTRL, 0x25), # Set cpw_en_oe and sw_ctrl_oe to 1
# DAC in "Programming" state now
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_INPUT_CONFIG, 0x80), # DAC input config - I2S, 32 bit
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_MASTER_MODE, 0x12), # DAC in synchronous mode
# Both channels volumes to full scale -0dBFS.
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_VOLUME1, 0x06),
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_VOLUME2, 0x06),
# Get DAC to HiFi state
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_HP_AMP_CTRL, 0x65), # Enable the Headphone amp
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x8A), # Set soft_start to 1
]
# USB connected event
EVT_USB_CONNECT = [
GPIO(GPIO_LED_A, HIGH),
]
# USB disconnected event
EVT_USB_DISCONNECT = [
GPIO(GPIO_LED_A, LOW),
]
# Audio streaming started event
EVT_STRM_START = [
GPIO(GPIO_LED_B, HIGH),
]
# Audio streaming stopped event
EVT_STRM_STOP = [
GPIO(GPIO_LED_B, LOW),
]
# Event on host selecting 48KHz sample rate
EVT_SEL_48K = [
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x0A), # Get DAC to "Programming" mode
DELAY_MS(100),
I2C_WRITE(SABRE9018Q2C_I2C_ADDR,SABRE9018Q2C_HP_AMP_CTRL, 0x25), # Set amp_en to '0'
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_OE_CTRL, 0xFD), # Disable the CLK0 and CLK2 outputs
# MCLK = 24.576MHz (48,96,192KHz)
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_CLK0_CTRL, 0x4D), # PLLA - source for MS0, MS0 - source of CLK0, 4mA drive strength
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS0_P1_UPPER, 0x05), # Set P1 divider
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS0_P2_LOWER, 0x00), # Write lower bits of P2 divider
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS2_R2_DIV, 0x30), # Change R2 divider to 8
DELAY_MS(1), # Delay for MultiSynth output to settle
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_OE_CTRL, 0xF8), # Enable all the clock outputs
I2C_WRITE(SABRE9018Q2C_I2C_ADDR,SABRE9018Q2C_INPUT_CONFIG, 0x80), # DAC input config - I2S - 32 bit
# Get DAC to HiFi state
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_HP_AMP_CTRL, 0x65), # Enable the Headphone amp
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x8A), # Set soft_start to 1
]
# Event on host selecting 96KHz sample rate
EVT_SEL_96K = [
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x0A), # Get DAC to "Programming" mode
DELAY_MS(100),
I2C_WRITE(SABRE9018Q2C_I2C_ADDR,SABRE9018Q2C_HP_AMP_CTRL, 0x25), # Set amp_en to '0'
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_OE_CTRL, 0xFD), # Disable the CLK0 and CLK2 outputs
# MCLK = 24.576MHz (48,96,192KHz)
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_CLK0_CTRL, 0x4D), # PLLA - source for MS0, MS0 - source of CLK0, 4mA drive strength
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS0_P1_UPPER, 0x05), # Set P1 divider
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS0_P2_LOWER, 0x00), # Write lower bits of P2 divider
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS2_R2_DIV, 0x20), # Change R2 divider to 4
DELAY_MS(1), # Delay for MultiSynth output to settle
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_OE_CTRL, 0xF8), # Enable all the clock outputs
I2C_WRITE(SABRE9018Q2C_I2C_ADDR,SABRE9018Q2C_INPUT_CONFIG, 0x80), # DAC input config - I2S - 32 bit
# Get DAC to HiFi state
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_HP_AMP_CTRL, 0x65), # Enable the Headphone amp
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x8A), # Set soft_start to 1
]
# Event on host selecting 192KHz sample rate
EVT_SEL_192K = [
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x0A), # Get DAC to "Programming" mode
DELAY_MS(100),
I2C_WRITE(SABRE9018Q2C_I2C_ADDR,SABRE9018Q2C_HP_AMP_CTRL, 0x25), # Set amp_en to '0'
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_OE_CTRL, 0xFD), # Disable the CLK0 and CLK2 outputs
# MCLK = 24.576MHz (48,96,192KHz)
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_CLK0_CTRL, 0x4D), # PLLA - source for MS0, MS0 - source of CLK0, 4mA drive strength
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS0_P1_UPPER, 0x05), # Set P1 divider
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS0_P2_LOWER, 0x00), # Write lower bits of P2 divider
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS2_R2_DIV, 0x10), # Change R2 divider to 2
DELAY_MS(1), # Delay for MultiSynth output to settle
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_OE_CTRL, 0xF8), # Enable all the clock outputs
I2C_WRITE(SABRE9018Q2C_I2C_ADDR,SABRE9018Q2C_INPUT_CONFIG, 0x80), # DAC input config - I2S - 32 bit
# Get DAC to HiFi state
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_HP_AMP_CTRL, 0x65), # Enable the Headphone amp
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x8A), # Set soft_start to 1
]
# Event on host selecting 384KHz sample rate
EVT_SEL_384K = [
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x0A), # Get DAC to "Programming" mode
DELAY_MS(100),
I2C_WRITE(SABRE9018Q2C_I2C_ADDR,SABRE9018Q2C_HP_AMP_CTRL, 0x25), # Set amp_en to '0'
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_OE_CTRL, 0xFD), # Disable the CLK0 and CLK2 outputs
# MCLK = 24.576MHz (48,96,192KHz)
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_CLK0_CTRL, 0x4D), # PLLA - source for MS0, MS0 - source of CLK0, 4mA drive strength
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS0_P1_UPPER, 0x05), # Set P1 divider
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS0_P2_LOWER, 0x00), # Write lower bits of P2 divider
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS2_R2_DIV, 0x00), # Change R2 divider to 1
DELAY_MS(1), # Delay for MultiSynth output to settle
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_OE_CTRL, 0xF8), # Enable all the clock outputs
I2C_WRITE(SABRE9018Q2C_I2C_ADDR,SABRE9018Q2C_INPUT_CONFIG, 0x80), # DAC input config - I2S - 32 bit
# Get DAC to HiFi state
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_HP_AMP_CTRL, 0x65), # Enable the Headphone amp
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x8A), # Set soft_start to 1
]
# Event on host selecting 44.1KHz sample rate
EVT_SEL_44_1K = [
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x0A), # Get DAC to "Programming" mode
DELAY_MS(100),
I2C_WRITE(SABRE9018Q2C_I2C_ADDR,SABRE9018Q2C_HP_AMP_CTRL, 0x25), # Set amp_en to '0'
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_OE_CTRL, 0xFD), # Disable the CLK0 and CLK2 outputs
# MCLK = 22.5792MHz (44.1,88.2,176.4kHz)
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_CLK0_CTRL, 0x6D), # PLLB - source for MS0, MS0 - source of CLK0, 4mA drive strength
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS0_P1_UPPER, 0x07), # Set P1 divider
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS0_P2_LOWER, 0x00), # Write lower bits of P2 divider
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS2_R2_DIV, 0x30), # Change R2 divider to 8
DELAY_MS(1), # Delay for MultiSynth output to settle
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_OE_CTRL, 0xF8), # Enable all the clock outputs
I2C_WRITE(SABRE9018Q2C_I2C_ADDR,SABRE9018Q2C_INPUT_CONFIG, 0x80), # DAC input config - I2S - 32 bit
# Get DAC to HiFi state
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_HP_AMP_CTRL, 0x65), # Enable the Headphone amp
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x8A), # Set soft_start to 1
]
# Event on host selecting 88.2KHz sample rate
EVT_SEL_88_2K = [
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x0A), # Get DAC to "Programming" mode
DELAY_MS(100),
I2C_WRITE(SABRE9018Q2C_I2C_ADDR,SABRE9018Q2C_HP_AMP_CTRL, 0x25), # Set amp_en to '0'
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_OE_CTRL, 0xFD), # Disable the CLK0 and CLK2 outputs
# MCLK = 24.576MHz (48,96,192KHz)
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_CLK0_CTRL, 0x6D), # PLLB - source for MS0, MS0 - source of CLK0, 4mA drive strength
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS0_P1_UPPER, 0x07), # Set P1 divider
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS0_P2_LOWER, 0x00), # Write lower bits of P2 divider
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS2_R2_DIV, 0x20), # Change R2 divider to 4
DELAY_MS(1), # Delay for MultiSynth output to settle
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_OE_CTRL, 0xF8), # Enable all the clock outputs
I2C_WRITE(SABRE9018Q2C_I2C_ADDR,SABRE9018Q2C_INPUT_CONFIG, 0x80), # DAC input config - I2S - 32 bit
# Get DAC to HiFi state
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_HP_AMP_CTRL, 0x65), # Enable the Headphone amp
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x8A), # Set soft_start to 1
]
# Event on host selecting 176.4KHz sample rate
EVT_SEL_176_4K = [
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x0A), # Get DAC to "Programming" mode
DELAY_MS(100),
I2C_WRITE(SABRE9018Q2C_I2C_ADDR,SABRE9018Q2C_HP_AMP_CTRL, 0x25), # Set amp_en to '0'
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_OE_CTRL, 0xFD), # Disable the CLK0 and CLK2 outputs
# MCLK = 24.576MHz (48,96,192KHz)
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_CLK0_CTRL, 0x6D), # PLLB - source for MS0, MS0 - source of CLK0, 4mA drive strength
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS0_P1_UPPER, 0x07), # Set P1 divider
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS0_P2_LOWER, 0x00), # Write lower bits of P2 divider
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS2_R2_DIV, 0x10), # Change R2 divider to 2
DELAY_MS(1), # Delay for MultiSynth output to settle
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_OE_CTRL, 0xF8), # Enable all the clock outputs
I2C_WRITE(SABRE9018Q2C_I2C_ADDR,SABRE9018Q2C_INPUT_CONFIG, 0x80), # DAC input config - I2S - 32 bit
# Get DAC to HiFi state
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_HP_AMP_CTRL, 0x65), # Enable the Headphone amp
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x8A), # Set soft_start to 1
]
# Event on host selecting 352.8KHz sample rate
EVT_SEL_352_8K = [
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x0A), # Get DAC to "Programming" mode
DELAY_MS(100),
I2C_WRITE(SABRE9018Q2C_I2C_ADDR,SABRE9018Q2C_HP_AMP_CTRL, 0x25), # Set amp_en to '0'
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_OE_CTRL, 0xFD), # Disable the CLK0 and CLK2 outputs
# MCLK = 24.576MHz (48,96,192KHz)
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_CLK0_CTRL, 0x6D), # PLLB - source for MS0, MS0 - source of CLK0, 4mA drive strength
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS0_P1_UPPER, 0x07), # Set P1 divider
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS0_P2_LOWER, 0x00), # Write lower bits of P2 divider
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS2_R2_DIV, 0x00), # Change R2 divider to 1
DELAY_MS(1), # Delay for MultiSynth output to settle
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_OE_CTRL, 0xF8), # Enable all the clock outputs
I2C_WRITE(SABRE9018Q2C_I2C_ADDR,SABRE9018Q2C_INPUT_CONFIG, 0x80), # DAC input config - I2S - 32 bit
# Get DAC to HiFi state
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_HP_AMP_CTRL, 0x65), # Enable the Headphone amp
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x8A), # Set soft_start to 1
]
# DSD active event
EVT_DSD_ACTIVE = [
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x0A), # Get DAC to "Programming" mode
DELAY_MS(100),
I2C_WRITE(SABRE9018Q2C_I2C_ADDR,SABRE9018Q2C_HP_AMP_CTRL, 0x25), # Set amp_en to '0'
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_OE_CTRL, 0xFD), # Disable the CLK0 and CLK2 outputs
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_CLK0_CTRL, 0x6D), # PLLB - source for MS0, MS0 - source of CLK0, 4mA drive strength
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS0_P1_UPPER, 0x07), # Set P1 divider
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS0_P2_LOWER, 0x00), # Write lower bits of P2 divider
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_MS2_R2_DIV, 0x00), # Change R2 divider to 1
DELAY_MS(1), # Delay for MultiSynth output to settle
I2C_WRITE(SI5351A_I2C_ADDR,SI5351A_OE_CTRL, 0xF8), # Enable all the clock outputs
I2C_WRITE(SABRE9018Q2C_I2C_ADDR,SABRE9018Q2C_INPUT_CONFIG, 0x83), # DAC input config - DSD
# Get DAC to HiFi state
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_HP_AMP_CTRL, 0x65), # Enable the Headphone amp
I2C_WRITE(SABRE9018Q2C_I2C_ADDR, SABRE9018Q2C_SOFT_START, 0x8A), # Set soft_start to 1
]
# PCM active event
EVT_PCM_ACTIVE = []
# Event on host selecting DSD128 format
EVT_SEL_DSD128 = []
# Event on host selecting DSD64 format
EVT_SEL_DSD64 = [] |
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