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楼主 |
发表于 2015-10-20 21:40:39
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我贴的这个代码,还是搞过at91sam的人才能看的明白吧
set_framebuffer(LCDD_BASE,lcd_buff+0x36);//lcd_buff+0x36);//首先开启DMA功能
//=========================================================
void set_framebuffer( uint8_t bLayer,void* pBuffer){
sLayer *pLD = pLayer(bLayer);
sLCDCDescriptor *pTD = &pLD->dmaD;
volatile uint32_t *pEnR = pEnableReg(bLayer);
volatile uint32_t *pDmaR = pHeadReg(bLayer);
volatile uint32_t *pStrR = pStrideReg(bLayer);
volatile uint32_t *pBlR = pBlenderReg(bLayer);
volatile uint32_t *pCfgR = pCfgReg(bLayer);
/** DMA is running, just add new descriptor to queue */
if (pBlR[0] & LCDC_BASECFG4_DMA)
{
pTD->addr = (uint32_t)pBuffer;
pTD->ctrl = LCDC_BASECTRL_DFETCH;
pTD->next = (uint32_t)pTD;
pDmaR[0] = (uint32_t)pTD;
pEnR[0] = LCDC_BASECHER_A2QEN;
}
else
{
/* 2. Write the channel descriptor (DSCR) structure in the system memory by
writing DSCR.CHXADDR Frame base address, DSCR.CHXCTRL channel control
and DSCR.CHXNEXT next descriptor location.
3. If more than one descriptor is expected, the DFETCH field of
DSCR.CHXCTRL is set to one to enable the descriptor fetch operation.
4. Write the DSCR.CHXNEXT register with the address location of the
descriptor structure and set DFETCH field of the DSCR.CHXCTRL register
to one. */
LCDD_SetDMA(pBuffer, pTD, (uint32_t)pDmaR);
}
/* Enable DMA */
if (pBuffer)
{
pBlR[0] |= LCDC_BASECFG4_DMA;
}
/* Enable & Update */
/* 5. Enable the relevant channel by writing one to the CHEN field of the
CHXCHER register. */
pEnR[0] = LCDC_BASECHER_UPDATEEN | LCDC_BASECHER_CHEN;
/* 6. An interrupt may be raised if unmasked when the descriptor has been
loaded. */
pLD->pBuffer = pBuffer;
}
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