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发表于 2015-6-9 21:03:12
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只用IRC48M,不用外部晶振,测试通过。
以下代码基于KSDK V1.1.0,MDK V5.13
注释来源于楼上,根据注释用寄存器操作实现
/*
Update clock divider, make sure core clock,
bus clock, flexbus clock and flash closk
is less than maximum support frequency
*/
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x01) |
SIM_CLKDIV1_OUTDIV4(0x03); /* Update system prescalers */
/* MCG_C2: RANGE = 3 */
/*Very high frequency range selected for the crystal oscillator*/
// MCG_BWR_C2_RANGE(MCG, 0x03);
MCG_C2 |= 0x30;
/*DRST_DRS default value 0x00,Reference Range: 32.768 kHz,DCO Range 24MHz*/
// MCG_BWR_DMX32(MCG, 1);
MCG_C4 |= 0x80;
/*
Switch to FEE mode
*/
/* FRDIV=6, RANGE=3, divide IRC48M with 1280 */
/* if FRDIV=7, RANGE=3, divide IRC48M with 1536,Final Core Freq 80MHz*/
// MCG_BWR_C1_FRDIV(MCG, 0x06);
// MCG_BWR_C1_FRDIV(MCG, 0x07);
MCG_C1 |= 0x38;
/* Switch to external reference clock*/
// MCG_BWR_C6_PLLS(MCG, 0);/*FLL is selected*/
MCG_C6 |= 0x40;
// MCG_BWR_C7_OSCSEL(MCG, 2); /* Enable IRC48M OSC*/
MCG_C7 |= 0x02;
// MCG_BWR_C1_IREFS(MCG, 0);/*External reference clock is selected*/
MCG_C1 &= ~0x04;
/*IREFST=1,Source of FLL reference clock is the internal reference clock*/
// while(MCG_BRD_S_IREFST(MCG));
while(MCG_S&0x10);
// MCG_BWR_DMX32(MCG, 0);/*Reference Range: 31.25–39.0625 kHz*/
MCG_C4 &= ~0x80;
// MCG_BWR_DRST_DRS(MCG, 3);/*DRST_DRS=0x03,DCO Range 96MHz*/
MCG_C4 |= 0x60;
有一个特殊之处是:将上面的代码替换system_MK22F51212.c中以下代码
原因是:MK22默认使用外部晶振,检测不到外部晶振,代码将在以下代码的第一个while死循环
MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
#if (MCG_MODE == MCG_MODE_PEE)
MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
#else
MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
#endif
if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
}
}
/* Check that the source of the FLL reference clock is the requested one. */
if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
}
} else {
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
}
}
MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
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